URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp5.xml] - Diff between revs 134 and 135

Show entire file | Details | Blame | View Log

Rev 134	Rev 135
Line 25...	Line 25...
`// You should have received a copy of the GNU Lesser General //`	`// You should have received a copy of the GNU Lesser General //`
`// Public License along with this source; if not, download it //`	`// Public License along with this source; if not, download it //`
`// from http://www.opencores.org/lgpl.shtml //`	`// from http://www.opencores.org/lgpl.shtml //`
`// //`	`// //`
`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`

`opencores.org`	`opencores.org`
`logic`	`logic`
`micro_bus`	`micro_bus`
`exp5 default`	`exp5`





`mb_out`	`mb_out`















`addr`

`addr_in`
`70`




`rdata`

`rdata_out`
`150`




`wdata`

`wdata_in`
`70`




`rd`

`rd_in`




`wr`

`wr_in`




`cs`

`cs_in`




`wait`	`addr`

`wait_out`	`addr_in`
`reg`	`70`




	`rdata`

	`rdata_out`
	`150`




	`wdata`

	`wdata_in`
	`70`




	`rd`

	`rd_in`




	`wr`

	`wr_in`




	`cs`

	`cs_in`



`mas_0`
	`wait`

	`wait_out`
	`reg`






`addr`

`mas_0_addr_out`
`30`




`rdata`

`mas_0_rdata_in`
`70`




`wdata`

`mas_0_wdata_out`
`70`





`rd`

`mas_0_rd_out`




`wr`

`mas_0_wr_out`




`cs`

`mas_0_cs_out`









	`mas_0`




`mas_1`







`addr`	`addr`

`mas_1_addr_out`	`mas_0_addr_out`
`30`	`30`




`rdata`	`rdata`

`mas_1_rdata_in`	`mas_0_rdata_in`
`70`	`70`




`wdata`	`wdata`

`mas_1_wdata_out`	`mas_0_wdata_out`
`70`	`70`




`rd`	`rd`

`mas_1_rd_out`	`mas_0_rd_out`




`wr`	`wr`

`mas_1_wr_out`	`mas_0_wr_out`




`cs`	`cs`

`mas_1_cs_out`	`mas_0_cs_out`

















`mas_2`








`addr`

`mas_2_addr_out`
`30`




`rdata`

`mas_2_rdata_in`
`70`




`wdata`

`mas_2_wdata_out`
`70`



	`mas_1`
`rd`

`mas_2_rd_out`




`wr`

`mas_2_wr_out`




`cs`

`mas_2_cs_out`




	`addr`

	`mas_1_addr_out`
	`30`




	`rdata`

	`mas_1_rdata_in`
	`70`




	`wdata`

	`mas_1_wdata_out`
	`70`




	`rd`

	`mas_1_rd_out`




	`wr`

	`mas_1_wr_out`



`mas_3`
	`cs`

	`mas_1_cs_out`






`addr`

`mas_3_addr_out`
`30`




`rdata`

`mas_3_rdata_in`
`70`




`wdata`

`mas_3_wdata_out`
`70`




`rd`

`mas_3_rd_out`




`wr`

`mas_3_wr_out`




`cs`

`mas_3_cs_out`










`mas_4`





	`mas_2`





`addr`

`mas_4_addr_out`
`30`




`rdata`

`mas_4_rdata_in`
`70`




`wdata`	`addr`

`mas_4_wdata_out`	`mas_2_addr_out`
`70`	`30`




`rd`	`rdata`

`mas_4_rd_out`	`mas_2_rdata_in`
	`70`




`wr`	`wdata`

`mas_4_wr_out`	`mas_2_wdata_out`
	`70`




`cs`	`rd`

`mas_4_cs_out`	`mas_2_rd_out`




	`wr`

	`mas_2_wr_out`




	`cs`

	`mas_2_cs_out`




















`gen_verilog`
`104.0`
`none`
`common`
`./tools/verilog/gen_verilog`


`destination`
`micro_bus_exp5`








	`mas_3`





`fs-common`




`../verilog/top.body.exp5`
`verilogSourcefragment`



	`addr`

	`mas_3_addr_out`
	`30`




`fs-sim`	`rdata`

	`mas_3_rdata_in`
	`70`




	`wdata`
`../verilog/copyright.v`
`verilogSourceinclude`	`mas_3_wdata_out`
	`70`




	`rd`

	`mas_3_rd_out`




	`wr`
`../verilog/common/micro_bus_exp5`
`verilogSourcemodule`	`mas_3_wr_out`




	`cs`

	`mas_3_cs_out`












`fs-syn`



`../verilog/copyright.v`
`verilogSourceinclude`






`../verilog/common/micro_bus_exp5`
`verilogSourcemodule`


	`mas_4`











	`addr`

	`mas_4_addr_out`
	`30`




	`rdata`

	`mas_4_rdata_in`
	`70`




	`wdata`

	`mas_4_wdata_out`
	`70`




	`rd`

	`mas_4_rd_out`




	`wr`

	`mas_4_wr_out`




	`cs`

	`mas_4_cs_out`













`verilog`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="verilog"/>`










`commoncommon`

`Verilog`


`fs-common`




`sim:Simulation:`

`Verilog`


`fs-sim`





`syn:Synthesis:`

`Verilog`


`fs-syn`





`doc`	`gen_verilog`
	`104.0`
	`none`
`spirit:library="Testbench"`	`:common:`
`spirit:name="toolflow"`	`tools/verilog/gen_verilog`
`spirit:version="documentation"/>`

`:Documentation:`	`destination`
`Verilog`	`micro_bus_exp5`













	`fs-common`

`clk`
`wire`
`in`	`../verilog/top.body.exp5`
	`verilogSourcefragment`




`reset`
`wire`	`fs-sim`
`in`




	`../verilog/copyright.v`
	`verilogSourceinclude`



`enable`
`wire`
`in`	`../verilog/common/micro_bus_exp5`
	`verilogSourcemodule`











	`fs-syn`



	`../verilog/copyright.v`
	`verilogSourceinclude`





`4`
`mb_out`
	`../verilog/common/micro_bus_exp5`
	`verilogSourcemodule`




`mas_0`
`0x00`





`mas_1`
`0x10`




`mas_2`
`0x20`




`mas_3`
`0x30`



`mas_4`
`0x40`








`mas_0`
`00`

`mas_0`
`16`
`8`




`mas_1`
`10`

`mas_1`
`16`
`8`





`mas_2`	`verilog`
`20`

`mas_2`	`ipxact:library="Testbench"`
`16`	`ipxact:name="toolflow"`
`8`	`ipxact:version="verilog"/>`







`mas_3`
`30`

`mas_3`
`16`
`8`




	`common:common:`

	`Verilog`
`mas_4`
`40`
	`fs-common`
`mas_4`
`16`
`8`




	`sim:Simulation:`

	`Verilog`


	`fs-sim`





	`syn:Synthesis:`

	`Verilog`


	`fs-syn`






	`doc`


	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="documentation"/>`

	`:Documentation:`
	`Verilog`









`mas_0`
`0x10`
`8`



`mas_1`
`0x10`
`8`


	`clk`
`mas_2`	`wire`
`0x10`	`in`
`8`



`mas_3`
`0x10`
`8`


	`reset`
`mas_4`	`wire`
`0x10`	`in`
`8`





	`enable`
	`wire`
	`in`















	`4`
	`mb_out`



	`mas_0`
	`0x00`




	`mas_1`
	`0x10`




	`mas_2`
	`0x20`




	`mas_3`
	`0x30`



	`mas_4`
	`0x40`







	`mas_0`
	`00`

	`mas_0`
	`16`
	`8`




	`mas_1`
	`10`

	`mas_1`
	`16`
	`8`





	`mas_2`
	`20`

	`mas_2`
	`16`
	`8`







	`mas_3`
	`30`

	`mas_3`
	`16`
	`8`





	`mas_4`
	`40`

	`mas_4`
	`16`
	`8`


















	`mas_0`
	`0x10`
	`8`



	`mas_1`
	`0x10`
	`8`



	`mas_2`
	`0x10`
	`8`



	`mas_3`
	`0x10`
	`8`



	`mas_4`
	`0x10`
	`8`

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp5.xml] - Diff between revs 134 and 135