URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [sim/] [testbenches/] [xml/] [ps2_interface_def_duth.design.xml] - Diff between revs 133 and 135

-Rev 133
+Rev 135
 Line 4...
 // Generated File Do Not EDIT                                                                         //
 //                                                                                                    //
 // ./tools/verilog/gen_tb -vendor opencores.org -library logic  -component ps2_interface  -version def //
 //                                                                                                    //
 -->
-xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
 xmlns:socgen="http://opencores.org"
 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
-xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
+xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
-http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 opencores.org
 logic
 ps2_interface
 def_duth.design
 busy
 clk
 ps2_clk_pad_in
 ps2_clk_pad_oe
 ps2_data_pad_in
 ps2_data_pad_oe
 reset
 rx_clear
 rx_data
 rx_frame_error
 rx_full
 rx_parity_cal
 rx_parity_error
 rx_parity_rcv
 rx_read
 tx_ack_error
 tx_buffer_empty
 tx_data
 tx_write
 dut
  CLK_HOLD_DELAY
  DATA_SETUP_DELAY
  DEBOUNCE_DELAY
  FREQ