URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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// Generated File Do Not EDIT //
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// Generated File Do Not EDIT //
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// //
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// //
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// ./tools/verilog/gen_tb -vendor opencores.org -library logic -component ps2_interface -version def //
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// ./tools/verilog/gen_tb -vendor opencores.org -library logic -component ps2_interface -version def //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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logic
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logic
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ps2_interface
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ps2_interface
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def_duth.design
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def_duth.design
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busy
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busy
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clk
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clk
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ps2_clk_pad_in
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ps2_clk_pad_in
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ps2_clk_pad_oe
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ps2_clk_pad_oe
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ps2_data_pad_in
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ps2_data_pad_in
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ps2_data_pad_oe
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ps2_data_pad_oe
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reset
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reset
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rx_clear
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rx_clear
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rx_data
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rx_data
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rx_frame_error
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rx_frame_error
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rx_full
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rx_full
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rx_parity_cal
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rx_parity_cal
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rx_parity_error
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rx_parity_error
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rx_parity_rcv
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rx_parity_rcv
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rx_read
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rx_read
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tx_ack_error
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tx_ack_error
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tx_buffer_empty
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tx_buffer_empty
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tx_data
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tx_data
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tx_write
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tx_write
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dut
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dut
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CLK_HOLD_DELAY
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CLK_HOLD_DELAY
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DATA_SETUP_DELAY
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DATA_SETUP_DELAY
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DEBOUNCE_DELAY
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DEBOUNCE_DELAY
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FREQ
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FREQ
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