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Line 25... |
// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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logic
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logic
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uart
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uart
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rx default
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rx
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slave_clk
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slave_clk
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clk
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clk
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clk
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clk
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slave_reset
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reset
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reset
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slave_reset
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reset
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reset
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uart
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txd_pad_out
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txd_pad_out
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rxd_pad_in
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rxd_pad_in
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uart
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txd_pad_out
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txd_pad_out
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rxd_data_avail
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rxd_pad_in
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rxd_pad_in
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IRQ
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rxd_data_avail_IRQ
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gen_verilog_sim
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104.0
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none
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:*Simulation:*
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./tools/verilog/gen_verilog
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destination
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uart_rx
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gen_verilog_syn
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104.0
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none
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:*Synthesis:*
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./tools/verilog/gen_verilog
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destination
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uart_rx
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fs-sim
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gen_verilog_sim
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104.0
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none
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:*Simulation:*
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tools/verilog/gen_verilog
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destination
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uart_rx
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gen_verilog_syn
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../verilog/copyright.v
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104.0
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verilogSourceinclude
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none
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:*Synthesis:*
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tools/verilog/gen_verilog
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destination
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uart_rx
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../verilog/sim/uart_rx
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verilogSourcemodule
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../verilog/top.body
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verilogSourcefragment
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../verilog/top.sim
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verilogSourcefragment
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dest_dir
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../views/sim/
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verilogSourcelibraryDir
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fs-sim
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../verilog/copyright.v
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verilogSourceinclude
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fs-syn
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../verilog/sim/uart_rx
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verilogSourcemodule
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../verilog/copyright.v
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../verilog/top.body
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verilogSourceinclude
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verilogSourcefragment
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../verilog/top.sim
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verilogSourcefragment
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../verilog/syn/uart_rx
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verilogSourcemodule
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dest_dir
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../verilog/top.body
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../views/sim/
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verilogSourcefragment
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verilogSourcelibraryDir
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dest_dir
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../views/syn/
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verilogSourcelibraryDir
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fs-syn
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../verilog/copyright.v
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verilogSourceinclude
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../verilog/syn/uart_rx
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verilogSourcemodule
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../verilog/top.body
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verilogSourcefragment
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dest_dir
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../views/syn/
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verilogSourcelibraryDir
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Hierarchical
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spirit:library="logic"
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spirit:name="uart"
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spirit:version="rx.design"/>
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verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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sim:*Simulation:*
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Hierarchical
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-syn
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doc
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="documentation"/>
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:*Documentation:*
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Verilog
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Hierarchical
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Hierarchical
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verilog
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="verilog"/>
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parity_enable
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wire
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in
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divider_in
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wire
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sim:*Simulation:*
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in
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DIV_SIZE-10
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cts_pad_in
|
Verilog
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wire
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in
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fs-sim
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rts_pad_out
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reg
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syn:*Synthesis:*
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out
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Verilog
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fs-syn
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doc
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="documentation"/>
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:*Documentation:*
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Verilog
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cts_out
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reg
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out
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rts_in
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wire
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in
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txd_parity
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wire
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in
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txd_force_parity
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wire
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in
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txd_load
|
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wire
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in
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txd_break
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wire
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in
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txd_data_in
|
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wire
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in
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SIZE-10
|
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txd_buffer_empty
|
|
wire
|
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out
|
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rxd_data_avail_stb
|
parity_enable
|
wire
|
wire
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in
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in
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rxd_data_avail
|
divider_in
|
wire
|
wire
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out
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in
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DIV_SIZE-10
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rxd_parity
|
cts_pad_in
|
wire
|
wire
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in
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in
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rxd_force_parity
|
rts_pad_out
|
wire
|
reg
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in
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out
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rxd_data_out
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wire
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out
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SIZE-10
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rxd_parity_error
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wire
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out
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rxd_stop_error
|
cts_out
|
wire
|
reg
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out
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out
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rts_in
|
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wire
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in
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txd_parity
|
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wire
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in
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txd_force_parity
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wire
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in
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txd_load
|
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wire
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in
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txd_break
|
|
wire
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in
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txd_data_in
|
|
wire
|
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in
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SIZE-10
|
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txd_buffer_empty
|
|
wire
|
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out
|
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rxd_data_avail_stb
|
|
wire
|
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in
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rxd_data_avail
|
|
wire
|
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out
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rxd_parity
|
|
wire
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in
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rxd_force_parity
|
|
wire
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in
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rxd_data_out
|
|
wire
|
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out
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SIZE-10
|
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rxd_parity_error
|
|
wire
|
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out
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rxd_stop_error
|
|
wire
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out
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