URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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// Generated File Do Not EDIT //
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// Generated File Do Not EDIT //
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// //
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// //
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// ./tools/verilog/gen_tb -vendor opencores.org -library logic -component uart -version rx //
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// ./tools/verilog/gen_tb -vendor opencores.org -library logic -component uart -version rx //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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logic
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logic
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uart
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uart
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rx_duth.design
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rx_duth.design
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clk
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clk
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cts_out
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cts_out
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cts_pad_in
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cts_pad_in
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divider_in
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divider_in
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parity_enable
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parity_enable
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reset
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reset
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rts_in
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rts_in
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rts_pad_out
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rts_pad_out
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rxd_data_avail
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rxd_data_avail
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rxd_data_avail_IRQ
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rxd_data_avail_stb
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rxd_data_avail_stb
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rxd_data_out
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rxd_data_out
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rxd_force_parity
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rxd_force_parity
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rxd_pad_in
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rxd_pad_in
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rxd_parity
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rxd_parity
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rxd_parity_error
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rxd_parity_error
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rxd_stop_error
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rxd_stop_error
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txd_break
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txd_break
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txd_buffer_empty
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txd_buffer_empty
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txd_data_in
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txd_data_in
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txd_force_parity
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txd_force_parity
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txd_load
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txd_load
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txd_pad_out
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txd_pad_out
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txd_parity
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txd_parity
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dut
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DIV
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dut
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DIV_SIZE
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PRESCALE
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PRE_SIZE
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DIV
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RX_FIFO_SIZE
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DIV_SIZE
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RX_FIFO_WORDS
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PRESCALE
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SIZE
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PRE_SIZE
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RX_FIFO_SIZE
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RX_FIFO_WORDS
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SIZE
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