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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [busDefs/] [abstractors/] [wb_b.4_rtl.xml] - Diff between revs 131 and 135

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//   Public License along with this source; if not, download it           //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
//                                                                        //
-->
-->
 
 
 
 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
 
opencores.org
opencores.org
wishbone
wishbone
wb
wb
b.4_rtl
b.4_rtl
 
 
 
 
  
  
 
 
   
   
      clk
      clk
      The clock input coordinates all activities for the internal logic within the WISHBONE interconnect. All WISHBONE output signals are registered at the rising edge of clk. All WISHBONE input signals are stable before the rising edge of clk.
      The clock input coordinates all activities for the internal logic within the WISHBONE interconnect. All WISHBONE output signals are registered at the rising edge of clk. All WISHBONE input signals are stable before the rising edge of clk.
      
      
        
        
          true
          true
        
        
        
        
          CLOCK
          CLOCK
          required
          required
          1
          1
          out
          out
        
        
        
        
          RESET
          RESET
          optional
          optional
          1
          1
          out
          out
        
        
        
        
          required
          required
          1
          1
          in
          in
        
        
        
        
          required
          required
          1
          1
          in
          in
        
        
        true
        true
      
      
    
    
 
 
    
    
      enable
      enable
      The enable input determines if a clk cycle should be acted upon or ignored for all operations including reset.
      The enable input determines if a clk cycle should be acted upon or ignored for all operations including reset.
      
      
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          required
          required
          1
          1
          out
          out
        
        
        
        
          optional
          optional
          1
          1
          in
          in
        
        
        
        
          optional
          optional
          1
          1
          in
          in
        
        
      
      
    
    
 
 
 
 
    
    
      rst
      rst
      The rst input forces the WISHBONE interface to restart. Furthermore, all internal self-starting state machines will be forced into an initial state. This signal only resets the WISHBONE interface. It is not required to reset other parts of an IP core (although it may be used that way).
      The rst input forces the WISHBONE interface to restart. Furthermore, all internal self-starting state machines will be forced into an initial state. This signal only resets the WISHBONE interface. It is not required to reset other parts of an IP core (although it may be used that way).
      
      
        
        
          true
          true
        
        
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          required
          required
          1
          1
          out
          out
        
        
        
        
          required
          required
          1
          1
          in
          in
        
        
        
        
          required
          required
          1
          1
          in
          in
        
        
        true
        true
      
      
    
    
 
 
 
 
 
 
    
    
      adr
      adr
      The adr output array is used to pass a binary address. The higher array boundary is specific to the address width of the core, and the lower array boundary is determined by the data port size and granularity. For example the array size on a 32-bit data port with BYTE granularity is adr[n:2]. In some cases (such as FIFO interfaces) the array may not be present on the interface.
      The adr output array is used to pass a binary address. The higher array boundary is specific to the address width of the core, and the lower array boundary is determined by the data port size and granularity. For example the array size on a 32-bit data port with BYTE granularity is adr[n:2]. In some cases (such as FIFO interfaces) the array may not be present on the interface.
      
      
        
        
          true
          true
        
        
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          out
          out
        
        
        
        
          required
          required
          in
          in
        
        
      
      
    
    
 
 
 
 
 
 
    
    
      cyc
      cyc
      The cycle output when asserted, indicates that a valid bus cycle is in progress. The signal is asserted for the duration of all bus cycles. For example, during a BLOCK transfer cycle there can be multiple data transfers. The signal is asserted during the first data transfer, and remains asserted until the last data transfer. The signal is useful for interfaces with multi-port interfaces (such as dual port memories). In these cases, the  signal requests use of a common bus from an arbiter.
      The cycle output when asserted, indicates that a valid bus cycle is in progress. The signal is asserted for the duration of all bus cycles. For example, during a BLOCK transfer cycle there can be multiple data transfers. The signal is asserted during the first data transfer, and remains asserted until the last data transfer. The signal is useful for interfaces with multi-port interfaces (such as dual port memories). In these cases, the  signal requests use of a common bus from an arbiter.
      
      
        
        
          true
          true
        
        
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          out
          out
        
        
        
        
          required
          required
          in
          in
        
        
      
      
    
    
 
 
 
 
 
 
 
 
 
 
    
    
      wdata
      wdata
      The data output array is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. wdata[63:0].Also see the rdata[] and sel[] signal descriptions.
      The data output array is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. wdata[63:0].Also see the rdata[] and sel[] signal descriptions.
      
      
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          out
          out
        
        
        
        
          required
          required
          in
          in
        
        
      
      
    
    
 
 
    
    
      rdata
      rdata
      The data input array is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. rdata[63:0]. Also see the wdata[] and sel[] signal descriptions.
      The data input array is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. rdata[63:0]. Also see the wdata[] and sel[] signal descriptions.
      
      
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          in
          in
        
        
        
        
          required
          required
          out
          out
        
        
      
      
    
    
 
 
 
 
   
   
      ack
      ack
      The acknowledge input  when asserted, indicates the normal termination of a bus cycle. Also see the err and rty signal descriptions.
      The acknowledge input  when asserted, indicates the normal termination of a bus cycle. Also see the err and rty signal descriptions.
      
      
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          in
          in
        
        
        
        
          required
          required
          out
          out
        
        
      
      
    
    
 
 
 
 
   
   
      err
      err
      The error input indicates an abnormal cycle termination. The source of the error, and the response generated by the MASTER is defined by the IP core supplier. Also see the ack and rty signal descriptions.
      The error input indicates an abnormal cycle termination. The source of the error, and the response generated by the MASTER is defined by the IP core supplier. Also see the ack and rty signal descriptions.
      
      
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          in
          in
        
        
        
        
          required
          required
          out
          out
        
        
      
      
    
    
 
 
 
 
   
   
      rty
      rty
      The retry input indicates that the interface is not ready to accept or send data, and that the cycle should be retried. When and how the cycle is retried is defined by the IP core supplier. Also see the ack and err signal descriptions.
      The retry input indicates that the interface is not ready to accept or send data, and that the cycle should be retried. When and how the cycle is retried is defined by the IP core supplier. Also see the ack and err signal descriptions.
      
      
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          in
          in
        
        
        
        
          required
          required
          out
          out
        
        
      
      
    
    
 
 
 
 
 
 
   
   
      stall
      stall
      The pipeline stall input indicates that current slave is not able to accept the transfer in the transaction queue. This signal is used in pipelined mode.
      The pipeline stall input indicates that current slave is not able to accept the transfer in the transaction queue. This signal is used in pipelined mode.
      
      
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          in
          in
        
        
        
        
          required
          required
          out
          out
        
        
      
      
    
    
 
 
 
 
 
 
 
 
 
 
   
   
      lock
      lock
      The lock output when asserted, indicates that the current bus cycle is uninterruptible. Lock is asserted to request complete ownership of the bus. Once the transfer has started, the INTERCON does not grant the bus to any other MASTER, until the current MASTER negates lock or cyc.
      The lock output when asserted, indicates that the current bus cycle is uninterruptible. Lock is asserted to request complete ownership of the bus. Once the transfer has started, the INTERCON does not grant the bus to any other MASTER, until the current MASTER negates lock or cyc.
      
      
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          out
          out
        
        
        
        
          required
          required
          in
          in
        
        
      
      
    
    
 
 
 
 
 
 
 
 
 
 
   
   
      sel
      sel
      The select output array indicates where valid data is expected on the rdata signal array during READ cycles, and where it is placed on the wdata signal array during WRITE cycles. The array boundaries are determined by the granularity of a port. For example, if 8-bit granularity is used on a 64-bit port, then there would be an array of eight select signals with boundaries of sel[7:0]. Each individual select signal correlates to one of eight active bytes on the 64-bit data port. For more information about sel, please refer to the data organization section in Chapter 3 of this specification. Also see the rdata[], wdata[] and stb signal descriptions.
      The select output array indicates where valid data is expected on the rdata signal array during READ cycles, and where it is placed on the wdata signal array during WRITE cycles. The array boundaries are determined by the granularity of a port. For example, if 8-bit granularity is used on a 64-bit port, then there would be an array of eight select signals with boundaries of sel[7:0]. Each individual select signal correlates to one of eight active bytes on the 64-bit data port. For more information about sel, please refer to the data organization section in Chapter 3 of this specification. Also see the rdata[], wdata[] and stb signal descriptions.
      
      
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          out
          out
        
        
        
        
          required
          required
          in
          in
        
        
      
      
    
    
 
 
 
 
 
 
 
 
   
   
      stb
      stb
      The strobe output indicates a valid data transfer cycle. It is used to qualify various other signals on the interface such as sel[]. The SLAVE asserts either the ack, err  or rty signals in response to every assertion of the stb signal.
      The strobe output indicates a valid data transfer cycle. It is used to qualify various other signals on the interface such as sel[]. The SLAVE asserts either the ack, err  or rty signals in response to every assertion of the stb signal.
      
      
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          out
          out
        
        
        
        
          required
          required
          in
          in
        
        
      
      
    
    
 
 
 
 
   
   
      wtgd
      wtgd
      Data tag type is used on MASTER and SLAVE interfaces. It contains information that is associated with the data input array wdata[], and is qualified by signal stb. For example, parity protection, error correction and time stamp information can be attached to the data bus. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is pre-defined by this specification. The name and operation of a data tag must be defined in the WISHBONE DATASHEET.
      Data tag type is used on MASTER and SLAVE interfaces. It contains information that is associated with the data input array wdata[], and is qualified by signal stb. For example, parity protection, error correction and time stamp information can be attached to the data bus. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is pre-defined by this specification. The name and operation of a data tag must be defined in the WISHBONE DATASHEET.
      
      
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          out
          out
        
        
        
        
          required
          required
          in
          in
        
        
      
      
    
    
 
 
 
 
 
 
 
 
   
   
      rtgd
      rtgd
      Data tag type is used on MASTER and SLAVE interfaces. It contains information that is associated with the data output array rdata[], and is qualified by signal stb. For example, parity protection, error correction and time stamp information can be attached to the data bus. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is pre-defined by this specification. The name and operation of a data tag must be defined in the WISHBONE DATASHEET.
      Data tag type is used on MASTER and SLAVE interfaces. It contains information that is associated with the data output array rdata[], and is qualified by signal stb. For example, parity protection, error correction and time stamp information can be attached to the data bus. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is pre-defined by this specification. The name and operation of a data tag must be defined in the WISHBONE DATASHEET.
      
      
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          in
          in
        
        
        
        
          required
          required
          out
          out
        
        
      
      
    
    
 
 
 
 
 
 
 
 
    
    
      tga
      tga
      Address tag type contains information associated with address lines adr[], and is qualified by signal stb. For example, address size (24-bit, 32-bit etc.) and memory management (protected vs. unprotected) information can be attached to an address. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is defined by this specification. The name and operation of an address tag must be defined in the WISHBONE DATASHEET.
      Address tag type contains information associated with address lines adr[], and is qualified by signal stb. For example, address size (24-bit, 32-bit etc.) and memory management (protected vs. unprotected) information can be attached to an address. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is defined by this specification. The name and operation of an address tag must be defined in the WISHBONE DATASHEET.
      
      
        
        
          true
          true
        
        
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          out
          out
        
        
        
        
          required
          required
          in
          in
        
        
      
      
    
    
 
 
 
 
 
 
    
    
      tgc
      tgc
      Cycle tag type  contains information associated with bus cycles, and is qualified by signal cyc. For example, data transfer, interrupt acknowledge and cache control cycles can be uniquely identified with the cycle tag. They can also be used to discriminate between WISHBONE SINGLE, BLOCK and RMW cycles. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is defined by this specification. The name and operation of a cycle tag must be defined in the WISHBONE DATASHEET.
      Cycle tag type  contains information associated with bus cycles, and is qualified by signal cyc. For example, data transfer, interrupt acknowledge and cache control cycles can be uniquely identified with the cycle tag. They can also be used to discriminate between WISHBONE SINGLE, BLOCK and RMW cycles. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is defined by this specification. The name and operation of a cycle tag must be defined in the WISHBONE DATASHEET.
      
      
        
        
          true
          true
        
        
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          out
          out
        
        
        
        
          required
          required
          in
          in
        
        
      
      
    
    
 
 
 
 
 
 
    
    
      we
      we
      The write enable output indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles.
      The write enable output indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles.
      
      
        
        
          true
          true
        
        
        
        
          CLOCK
          CLOCK
          illegal
          illegal
        
        
        
        
          ENABLE
          ENABLE
          illegal
          illegal
        
        
        
        
          RESET
          RESET
          illegal
          illegal
        
        
        
        
          required
          required
          out
          out
        
        
        
        
          required
          required
          in
          in
        
        
      
      
    
    
 
 
 
 
 
 
 
 
  
  
 
 
 
 
 
 
 
 
 
 
 
 

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