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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [rtl/] [xml/] [wb_memory_def.design.xml] - Diff between revs 134 and 135

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Rev 134 Rev 135
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//   You should have received a copy of the GNU Lesser General            //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
//                                                                        //
-->
-->
 
 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
 
opencores.org
opencores.org
wishbone
wishbone
wb_memory
wb_memory
def.design
def.design
 
 
 
 
 
 
 
 
 
 
 
 
 
 
    
    
      clk_i
      clk_i
      
      
      
      
      
      
      
      
      
      
    
    
 
 
 
 
 
 
   
   
      sel_i
      sel_i
      
      
      
      
    
    
 
 
   
   
      sel_i
      sel_i
      
      
      
      
    
    
 
 
   
   
      sel_i
      sel_i
      
      
      
      
    
    
 
 
   
   
      sel_i
      sel_i
      
      
      
      
    
    
 
 
 
 
    
    
      dat_i
      dat_i
      
      
      
      
    
    
 
 
    
    
      dat_i
      dat_i
      
      
      
      
    
    
 
 
    
    
      dat_i
      dat_i
      
      
      
      
    
    
 
 
    
    
      dat_i
      dat_i
      
      
      
      
    
    
 
 
 
 
    
    
      dat_o
      dat_o
      
      
      
      
    
    
 
 
    
    
      dat_o
      dat_o
      
      
      
      
    
    
 
 
    
    
      dat_o
      dat_o
      
      
      
      
    
    
 
 
    
    
      dat_o
      dat_o
      
      
      
      
    
    
 
 
 
 
 
 
 
 
    
    
      adr_i
      adr_i
      
      
      
      
      
      
      
      
      
      
    
    
 
 
 
 
    
    
      sram_wr
      sram_wr
      
      
      
      
      
      
      
      
      
      
    
    
 
 
 
 
   
   
      
      
      
      
      
      
      
      
      
      
      
      
      
      
      
      
    
    
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
rambyte_0
rambyte_0
 
 
 
 
adr_width
adr_width
mem_size
mem_size
0
0
 
 
 
 
 
 
 
 
 
 
rambyte_1
rambyte_1
 
 
 
 
adr_width
adr_width
mem_size
mem_size
0
0
 
 
 
 
 
 
 
 
 
 
rambyte_2
rambyte_2
 
 
 
 
adr_width
adr_width
mem_size
mem_size
0
0
 
 
 
 
 
 
 
 
 
 
rambyte_3
rambyte_3
 
 
 
 
adr_width
adr_width
mem_size
mem_size
0
0
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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