URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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wishbone
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wishbone
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wb_model
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wb_model
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master default
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master
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wb
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wb
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adr
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adr
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wb_addr_width-10
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adr
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adr
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wb_addr_width-10
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wdata
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dout
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wb_data_width-10
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wdata
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dout
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wb_data_width-10
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rdata
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din
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wb_data_width-10
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rdata
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din
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wb_data_width-10
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sel
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sel
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sel
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sel
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ack
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ack
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ack
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ack
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cyc
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cyc
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cyc
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cyc
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stb
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stb
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stb
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stb
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we
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we
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we
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we
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gen_verilogLib_sim
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105.0
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none
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:*Simulation:*
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./tools/verilog/gen_verilogLib
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dest_dir
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../views
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view
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sim
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gen_verilogLib_syn
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105.0
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none
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:*Synthesis:*
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./tools/verilog/gen_verilogLib
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dest_dir
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../views
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view
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syn
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gen_verilogLib_sim
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105.0
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none
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:*Simulation:*
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tools/verilog/gen_verilogLib
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dest_dir
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../views
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view
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sim
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gen_verilogLib_syn
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105.0
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none
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:*Synthesis:*
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tools/verilog/gen_verilogLib
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dest_dir
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../views
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view
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syn
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fs-sim
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../verilog/copyright.v
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verilogSourceinclude
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../verilog/top.sim
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verilogSourcemodule
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fs-syn
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verilog
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verilog
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wb_model_master
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awidth
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32
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dwidth
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32
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fs-sim
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../verilog/copyright.v
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verilogSourceinclude
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../verilog/top.syn
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verilogSourcemodule
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dest_dir../views/syn/
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verilogSourcelibraryDir
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rtl
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verilog:Kactus2:
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verilog
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-syn
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doc
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="documentation"/>
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:*Documentation:*
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Verilog
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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dwidth32
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awidth32
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Verilog
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fs-syn
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clk
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wire
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in
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reset
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doc
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wire
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in
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="documentation"/>
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:*Documentation:*
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Verilog
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adr
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reg
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out
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awidth-10
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dout
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reg
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out
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dwidth0
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dwidth32
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awidth32
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cyc
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reg
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out
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clk
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stb
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wire
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reg
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in
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out
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reset
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we
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wire
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reg
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in
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out
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adr
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reg
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out
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awidth-10
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sel
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reg
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out
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dwidth/8-10
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dout
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reg
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out
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dwidth0
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din
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wire
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in
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dwidth-10
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cyc
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reg
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out
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stb
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ack
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reg
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wire
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out
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in
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we
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err
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reg
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wire
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out
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in
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rty
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wire
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in
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sel
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reg
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out
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dwidth/8-10
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din
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wire
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in
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dwidth-10
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ack
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wire
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in
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err
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wire
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in
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rty
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wire
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in
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fs-sim
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../verilog/copyright.v
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verilogSourceinclude
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../verilog/top.sim
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verilogSourcemodule
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fs-syn
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../verilog/copyright.v
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verilogSourceinclude
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../verilog/top.syn
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verilogSourcemodule
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dest_dir../views/syn/
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verilogSourcelibraryDir
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© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.