| Line 25... |
Line 25... |
// You should have received a copy of the GNU Lesser General //
|
// You should have received a copy of the GNU Lesser General //
|
// Public License along with this source; if not, download it //
|
// Public License along with this source; if not, download it //
|
// from http://www.opencores.org/lgpl.shtml //
|
// from http://www.opencores.org/lgpl.shtml //
|
// //
|
// //
|
-->
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
wishbone
|
wishbone
|
wb_uart16550
|
wb_uart16550
|
def default
|
def
|
|
|
|
|
|
|
|
|
|
|
|
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wb_clk
|
wb_clk
|
|
|
|
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|
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|
clk
|
|
wb_clk_i
|
clk
|
|
wb_clk_i
|
|
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wb_reset
|
wb_reset
|
|
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|
|
reset
|
|
wb_rst_i
|
reset
|
|
wb_rst_i
|
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|
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|
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|
|
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wb
|
wb
|
|
|
|
|
little
|
|
8
|
|
|
|
|
|
|
|
|
|
adr
|
|
|
|
wb_adr_i
|
|
WB_ADDR_WIDTH-10
|
|
|
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|
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adr
|
|
|
|
wb_adr_i
|
|
WB_ADDR_WIDTH-10
|
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|
|
|
|
|
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|
wdata
|
|
|
|
wb_dat_i
|
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WB_DATA_WIDTH-10
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wdata
|
|
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|
wb_dat_i
|
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WB_DATA_WIDTH-10
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rdata
|
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wb_dat_o
|
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WB_DATA_WIDTH-10
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rdata
|
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wb_dat_o
|
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WB_DATA_WIDTH-10
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sel
|
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wb_sel_i
|
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sel
|
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wb_sel_i
|
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ack
|
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wb_ack_o
|
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ack
|
|
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wb_ack_o
|
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cyc
|
|
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|
wb_cyc_i
|
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cyc
|
|
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|
wb_cyc_i
|
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|
stb
|
|
|
|
wb_stb_i
|
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stb
|
|
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|
wb_stb_i
|
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|
we
|
|
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|
wb_we_i
|
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we
|
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wb_we_i
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|
little
|
|
8
|
|
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|
gen_registers
|
|
102.1
|
|
none
|
|
common
|
|
./tools/regtool/gen_registers
|
|
|
|
|
|
bus_intf
|
|
wb
|
|
|
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|
dest_dir
|
|
../verilog
|
|
|
|
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|
|
|
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|
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|
|
|
gen_verilog
|
gen_registers
|
104.0
|
102.1
|
none
|
none
|
common
|
:*common:*
|
./tools/verilog/gen_verilog
|
tools/regtool/gen_registers
|
|
|
|
|
destination
|
bus_intf
|
wb_uart16550_def
|
wb
|
|
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dest_dir
|
|
../verilog
|
|
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|
gen_verilog
|
|
104.0
|
|
none
|
|
:*common:*
|
|
tools/verilog/gen_verilog
|
|
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destination
|
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wb_uart16550_def
|
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|
fs-sim
|
|
|
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|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
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|
../verilog/common/wb_uart16550_def
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|
verilogSourcemodule
|
|
|
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|
fs-sim
|
../verilog/defines
|
|
verilogSourceinclude
|
|
|
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|
|
|
|
|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
wb
|
|
../verilog/wb_uart16550_def_wb
|
../verilog/common/wb_uart16550_def
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
../verilog/defines
|
|
verilogSourceinclude
|
|
|
|
|
|
|
raminfr
|
|
../verilog/raminfr
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
receiver
|
wb
|
../verilog/receiver
|
../verilog/wb_uart16550_def_wb
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
regs
|
|
../verilog/regs
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
rfifo
|
raminfr
|
../verilog/rfifo
|
../verilog/raminfr
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
sync_flops
|
receiver
|
../verilog/sync_flops
|
../verilog/receiver
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
tfifo
|
regs
|
../verilog/tfifo
|
../verilog/regs
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
transmitter
|
rfifo
|
../verilog/transmitter
|
../verilog/rfifo
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
wb_fsm
|
sync_flops
|
../verilog/wb_fsm
|
../verilog/sync_flops
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
|
tfifo
|
|
../verilog/tfifo
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
transmitter
|
|
../verilog/transmitter
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
wb_fsm
|
|
../verilog/wb_fsm
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/common/wb_uart16550_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
fs-syn
|
../verilog/defines
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
wb
|
|
../verilog/wb_uart16550_def_wb
|
../verilog/copyright.v
|
verilogSourcemodule
|
verilogSourceinclude
|
|
|
|
|
|
|
raminfr
|
|
../verilog/raminfr
|
../verilog/common/wb_uart16550_def
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
receiver
|
|
../verilog/receiver
|
../verilog/defines
|
verilogSourcemodule
|
verilogSourceinclude
|
|
|
|
|
|
|
regs
|
wb
|
../verilog/regs
|
../verilog/wb_uart16550_def_wb
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
rfifo
|
raminfr
|
../verilog/rfifo
|
../verilog/raminfr
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
sync_flops
|
receiver
|
../verilog/sync_flops
|
../verilog/receiver
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
tfifo
|
regs
|
../verilog/tfifo
|
../verilog/regs
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
transmitter
|
rfifo
|
../verilog/transmitter
|
../verilog/rfifo
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
wb_fsm
|
sync_flops
|
../verilog/wb_fsm
|
../verilog/sync_flops
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
|
tfifo
|
|
../verilog/tfifo
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
transmitter
|
|
../verilog/transmitter
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
wb_fsm
|
|
../verilog/wb_fsm
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
../verilog/top.body
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
../verilog/top.body
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
commoncommon
|
|
|
|
Verilog
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
|
|
|
|
|
common:*common:*
|
|
|
|
Verilog
|
sim:*Simulation:*
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
Verilog
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
|
|
Verilog
|
|
|
sim:*Simulation:*
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
Verilog
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
baud_o
|
|
wire
|
|
out
|
|
|
|
|
|
cts_pad_i
|
|
wire
|
|
in
|
|
|
|
|
|
dcd_pad_i
|
|
wire
|
|
in
|
|
|
|
|
|
dsr_pad_i
|
baud_o
|
wire
|
wire
|
in
|
out
|
|
|
|
|
dtr_pad_o
|
cts_pad_i
|
wire
|
wire
|
out
|
in
|
|
|
|
|
int_o
|
dcd_pad_i
|
wire
|
wire
|
out
|
in
|
|
|
|
|
|
dsr_pad_i
|
|
wire
|
|
in
|
|
|
|
|
ri_pad_i
|
dtr_pad_o
|
wire
|
wire
|
in
|
out
|
|
|
|
|
rts_pad_o
|
int_o
|
wire
|
wire
|
out
|
out
|
|
|
|
|
srx_pad_i
|
|
wire
|
|
in
|
|
|
|
|
|
stx_pad_o
|
ri_pad_i
|
wire
|
wire
|
out
|
in
|
|
|
|
|
|
rts_pad_o
|
|
wire
|
|
out
|
|
|
|
|
|
srx_pad_i
|
|
wire
|
|
in
|
|
|
|
|
|
stx_pad_o
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
8
|
|
wb
|
|
|
|
wb
|
|
0x00
|
|
|
|
|
|
|
|
|
|
|
8
|
|
wb
|
|
|
|
wb
|
|
0x00
|
|
|
|
|
mb_microbus
|
|
0x100
|
|
8
|
|
|
|
|
|
|
|
rb_dll_reg
|
|
0x0
|
|
8
|
|
read-only
|
|
|
|
|
|
|
|
|
mb_microbus
|
|
0x100
|
|
8
|
|
|
|
|
tr_reg
|
|
0x0
|
|
8
|
|
write-strobe
|
|
|
|
|
|
|
|
|
rb_dll_reg
|
|
0x0
|
|
8
|
|
read-only
|
|
|
|
|
|
|
ie_dlh_reg
|
|
0x1
|
|
8
|
|
read-only
|
|
|
|
|
|
|
|
ie_reg
|
tr_reg
|
0x1
|
0x0
|
4
|
8
|
write-strobe
|
write-strobe
|
|
|
|
|
|
|
|
|
|
ie_dlh_reg
|
|
0x1
|
|
8
|
|
read-only
|
|
|
|
|
|
|
|
ie_reg
|
|
0x1
|
|
4
|
|
write-strobe
|
|
|
|
|
|
|
dll_reg
|
|
0x0
|
|
8
|
|
write-strobe
|
|
|
|
|
|
|
|
|
|
dlh_reg
|
|
0x1
|
|
8
|
|
write-strobe
|
|
|
|
|
|
|
|
|
dll_reg
|
|
0x0
|
|
8
|
|
write-strobe
|
|
|
|
|
|
|
|
|
|
dlh_reg
|
|
0x1
|
|
8
|
|
write-strobe
|
|
|
|
|
|
|
ii_reg
|
|
0x2
|
|
4
|
|
read-only
|
|
|
|
|
|
|
|
fc_reg
|
|
0x2
|
|
8
|
|
write-only
|
|
|
|
|
|
|
|
lc_reg
|
|
0x3
|
|
8
|
|
read-write
|
|
|
|
bits
|
|
Bits in character
|
|
0
|
|
2
|
|
|
|
|
|
sb
|
|
Stop bits
|
|
2
|
|
1
|
|
|
|
|
|
pe
|
|
Parity enable
|
|
3
|
|
1
|
|
|
|
|
|
ep
|
|
Even parity
|
|
4
|
|
1
|
|
|
|
|
|
sp
|
|
Stick parity
|
|
5
|
|
1
|
|
|
|
|
|
bc
|
|
Break control
|
|
6
|
|
1
|
|
|
|
|
|
dlab
|
|
Divsior latch access bit
|
|
7
|
|
1
|
|
|
|
|
|
|
|
|
ii_reg
|
|
0x2
|
|
4
|
|
read-only
|
|
|
|
|
|
|
mc_reg
|
fc_reg
|
0x4
|
0x2
|
5
|
8
|
read-write
|
write-only
|
|
|
dtr
|
|
Data transmit ready
|
|
0
|
|
1
|
|
|
|
|
|
rts
|
|
Ready to Send
|
|
1
|
|
1
|
|
|
|
|
|
out
|
|
Output control
|
|
2
|
|
2
|
|
|
|
|
|
loopback
|
|
loopback control
|
|
4
|
|
1
|
|
|
|
|
|
|
|
|
|
ls_reg
|
lc_reg
|
0x5
|
0x3
|
8
|
8
|
read-only
|
read-write
|
|
|
|
bits
|
|
Bits in character
|
|
0
|
|
2
|
|
|
|
|
|
sb
|
|
Stop bits
|
|
2
|
|
1
|
|
|
|
|
|
pe
|
|
Parity enable
|
|
3
|
|
1
|
|
|
|
|
|
ep
|
|
Even parity
|
|
4
|
|
1
|
|
|
|
|
|
sp
|
|
Stick parity
|
|
5
|
|
1
|
|
|
|
|
|
bc
|
|
Break control
|
|
6
|
|
1
|
|
|
|
|
|
dlab
|
|
Divsior latch access bit
|
|
7
|
|
1
|
|
|
|
|
|
|
ms_reg
|
|
0x6
|
|
8
|
|
read-only
|
|
|
|
|
|
|
|
sr_reg
|
mc_reg
|
0x7
|
0x4
|
8
|
5
|
read-write
|
read-write
|
|
|
|
dtr
|
|
Data transmit ready
|
|
0
|
|
1
|
|
|
|
|
|
rts
|
|
Ready to Send
|
|
1
|
|
1
|
|
|
|
|
|
out
|
|
Output control
|
|
2
|
|
2
|
|
|
|
|
|
loopback
|
|
loopback control
|
|
4
|
|
1
|
|
|
|
|
|
|
|
|
|
ls_reg
|
|
0x5
|
|
8
|
|
read-only
|
|
|
|
|
|
|
|
ms_reg
|
|
0x6
|
|
8
|
|
read-only
|
|
|
|
|
|
|
debug_0_reg
|
sr_reg
|
0x8
|
0x7
|
32
|
8
|
read-only
|
read-write
|
|
|
|
|
|
|
|
|
debug_1_reg
|
|
0xc
|
|
32
|
|
read-only
|
|
|
|
|
|
|
|
|
debug_0_reg
|
|
0x8
|
|
32
|
|
read-only
|
|
|
|
|
|
|
|
|
|
debug_1_reg
|
|
0xc
|
|
32
|
|
read-only
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
