URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_lit_duth.design.xml] - Diff between revs 134 and 135

-Rev 134
+Rev 135
 Line 4...
 // Generated File Do Not EDIT                                                                         //
 //                                                                                                    //
 // ./tools/verilog/gen_tb -vendor opencores.org -library wishbone  -component wb_uart16550  -version bus32_lit //
 //                                                                                                    //
 -->
-xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
 xmlns:socgen="http://opencores.org"
 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
-xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
+xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
-http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 opencores.org
 wishbone
 wb_uart16550
 bus32_lit_duth.design
 baud_o
 cts_pad_i
 dcd_pad_i
 dsr_pad_i
 dtr_pad_o
 int_o
 ri_pad_i
 rts_pad_o
 srx_pad_i
 stx_pad_o
 wb_ack_o
 wb_adr_i
 wb_clk_i
 wb_cyc_i
 wb_dat_i
 wb_dat_o
 wb_rst_i
 wb_sel_i
 wb_stb_i
 wb_we_i
 dut
  PRESCALER_PRESET
  WB_ADDR_WIDTH
  WB_BYTE_LANES
  WB_DATA_WIDTH