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Line 25... |
// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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Testbench
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Testbench
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or1200_dbg_model
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or1200_dbg_model
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def default
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def
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debug
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debug
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addr
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dbg_adr_i
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310
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reg
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wdata
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dbg_dat_i
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310
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reg
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rdata
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addr
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dbg_dat_o
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dbg_adr_i
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310
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310
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reg
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lss
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wdata
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dbg_lss_o
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dbg_dat_i
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30
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310
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reg
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is
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rdata
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dbg_is_o
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dbg_dat_o
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10
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310
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wp
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lss
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dbg_wp_o
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dbg_lss_o
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100
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30
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is
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dbg_is_o
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10
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stall
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wp
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dbg_stall_i
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reg
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dbg_wp_o
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100
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ewt
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dbg_ewt_i
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reg
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bp
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stall
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dbg_bp_o
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dbg_stall_i
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reg
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stb
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ewt
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dbg_stb_i
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dbg_ewt_i
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reg
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reg
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we
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bp
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dbg_we_i
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dbg_bp_o
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reg
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ack
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stb
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dbg_ack_o
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dbg_stb_i
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reg
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we
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dbg_we_i
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reg
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ack
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dbg_ack_o
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gen_verilog_sim
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104.0
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none
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:*Simulation:*
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./tools/verilog/gen_verilog
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destination
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top.out.sim
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dest_dir
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../verilog
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gen_verilog_syn
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104.0
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none
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:*Synthesis:*
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./tools/verilog/gen_verilog
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destination
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top.out.syn
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dest_dir
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../verilog
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gen_verilogLib_sim
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105.0
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none
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:*Simulation:*
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./tools/verilog/gen_verilogLib
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dest_dir
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../views
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view
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sim
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gen_verilogLib_syn
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105.0
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none
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:*Synthesis:*
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./tools/verilog/gen_verilogLib
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dest_dir
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../views
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view
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syn
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gen_verilog_sim
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104.0
|
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none
|
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:*Simulation:*
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tools/verilog/gen_verilog
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destination
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top.out.sim
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dest_dir
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../verilog
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fs-sim
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gen_verilog_syn
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104.0
|
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none
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:*Synthesis:*
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tools/verilog/gen_verilog
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destination
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top.out.syn
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dest_dir
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../verilog
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../verilog/copyright.v
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verilogSourceinclude
|
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../verilog/sim/top.out.sim
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verilogSourcemodule
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gen_verilogLib_sim
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105.0
|
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none
|
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:*Simulation:*
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tools/verilog/gen_verilogLib
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dest_dir
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../views
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view
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sim
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../verilog/top.task
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verilogSourcefragment
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gen_verilogLib_syn
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105.0
|
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none
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:*Synthesis:*
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tools/verilog/gen_verilogLib
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dest_dir
|
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../views
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view
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syn
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dest_dir../views/sim/
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verilogSourcelibraryDir
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fs-sim
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../verilog/copyright.v
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verilogSourceinclude
|
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../verilog/sim/top.out.sim
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|
verilogSourcemodule
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fs-syn
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../verilog/copyright.v
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../verilog/top.task
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verilogSourceinclude
|
verilogSourcefragment
|
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../verilog/syn/top.out.syn
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|
verilogSourcemodule
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dest_dir../views/syn/
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verilogSourcelibraryDir
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dest_dir../views/sim/
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verilogSourcelibraryDir
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fs-syn
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../verilog/copyright.v
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|
verilogSourceinclude
|
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../verilog/syn/top.out.syn
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|
verilogSourcemodule
|
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dest_dir../views/syn/
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verilogSourcelibraryDir
|
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sim:*Simulation:*
|
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|
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Verilog
|
|
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fs-sim
|
|
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syn:*Synthesis:*
|
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|
Verilog
|
|
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fs-syn
|
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doc
|
|
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|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
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OUT_WIDTH10
|
|
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clk
|
|
wire
|
sim:*Simulation:*
|
in
|
|
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reset
|
Verilog
|
wire
|
|
in
|
|
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fs-sim
|
|
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|
syn:*Synthesis:*
|
|
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|
Verilog
|
|
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fs-syn
|
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doc
|
|
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|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
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OUT_WIDTH10
|
|
|
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clk
|
|
wire
|
|
in
|
|
|
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reset
|
|
wire
|
|
in
|
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