URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [mt45w8mw12/] [rtl/] [xml/] [mt45w8mw12_def.xml] - Diff between revs 134 and 135

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-Rev 134
+Rev 135
 Line 25...
 //   You should have received a copy of the GNU Lesser General            //
 //   Public License along with this source; if not, download it           //
 //   from http://www.opencores.org/lgpl.shtml                             //
 //                                                                        //
 -->
-xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
 xmlns:socgen="http://opencores.org"
 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
-xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
+xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
-http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
+http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 opencores.org
 Testbench
 mt45w8mw12
-def  default
+def
   gen_verilogLib_sim
 .0
   none
   :*Simulation:*
-  ./tools/verilog/gen_verilogLib
+  tools/verilog/gen_verilogLib
       dest_dir
       ../views
       view
       sim
   gen_verilogLib_syn
 .0
   none
   :*Synthesis:*
-  ./tools/verilog/gen_verilogLib
+  tools/verilog/gen_verilogLib
       dest_dir
       ../views
       view
       syn
       fs-sim
         ../verilog/copyright.v
         verilogSourceinclude
         ../verilog/top.sim
         verilogSourcemodule
         dest_dir../views/sim/
         verilogSourcelibraryDir
       fs-syn
         ../verilog/copyright.v
         verilogSourceinclude
         ../verilog/top.syn
         verilogSourcemodule
         dest_dir../views/syn/
         verilogSourcelibraryDir
               sim:*Simulation:*
               Verilog
                             fs-sim
               syn:*Synthesis:*
               Verilog
                             fs-syn
               doc
-                                   spirit:library="Testbench"
+                                   ipxact:library="Testbench"
-                                   spirit:name="toolflow"
+                                   ipxact:name="toolflow"
-                                   spirit:version="documentation"/>
+                                   ipxact:version="documentation"/>
               :*Documentation:*
               Verilog
 ADDR_BITS23
 DQ_BITS16
 MEM_BITS16
 clk
 wire
 in
 adv_n
 wire
 in
 cre
 wire
 in
 o_wait
 wire
 out
 ce_n
 wire
 in
 oe_n
 wire
 in
 we_n
 wire
 in
 lb_n
 wire
 in
 ub_n
 wire
 in
 addr
 wire
 in
 ADDR_BITS-10
 dq
 wire
 inout
 DQ_BITS-10
 Line 272...

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [mt45w8mw12/] [rtl/] [xml/] [mt45w8mw12_def.xml] - Diff between revs 134 and 135