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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [xml/] [cde_clock_testmux.xml] - Diff between revs 131 and 135

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Rev 131 Rev 135
Line 1... Line 1...
 
 
 
 
 
 
-->
-->
 
 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
 
opencores.org
opencores.org
cde
cde
clock
clock
testmux  default
testmux
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   
   
      fs-sim
      fs-sim
 
 
 
 
      
      
        dest_dir
        dest_dir
        ../verilog/
        ../verilog/
        verilogSourcelibraryDir
        verilogSourcelibraryDir
      
      
 
 
  
  
 
 
 
 
   
   
      fs-syn
      fs-syn
 
 
      
      
        dest_dir
        dest_dir
        ../verilog/
        ../verilog/
        verilogSourcelibraryDir
        verilogSourcelibraryDir
      
      
 
 
 
 
 
 
   
   
 
 
 
 
    
    
 
 
      fs-lint
      fs-lint
      
      
        dest_dir
        dest_dir
        ../verilog/
        ../verilog/
        verilogSourcelibraryDir
        verilogSourcelibraryDir
      
      
 
 
    
    
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
       
       
 
 
 
 
              
              
              sim:*Simulation:*
              sim:*Simulation:*
              Verilog
              Verilog
              
              
                     
                     
                            fs-sim
                            fs-sim
                     
                     
              
              
 
 
              
              
              syn:*Synthesis:*
              syn:*Synthesis:*
              Verilog
              Verilog
              
              
                     
                     
                            fs-syn
                            fs-syn
                     
                     
              
              
 
 
 
 
            
            
              doc
              doc
              
              
              
              
                                   spirit:library="Testbench"
                                   ipxact:library="Testbench"
                                   spirit:name="toolflow"
                                   ipxact:name="toolflow"
                                   spirit:version="documentation"/>
                                   ipxact:version="documentation"/>
              
              
              :*Documentation:*
              :*Documentation:*
              Verilog
              Verilog
              
              
 
 
 
 
 
 
 
 
      
      
 
 
 
 
 
 
 
 
 
 
 
 
sel
sel
wire
wire
in
in
 
 
 
 
clk_0
clk_0
wire
wire
in
in
 
 
 
 
clk_1
clk_1
wire
wire
in
in
 
 
 
 
 
 
 
 
clk_out
clk_out
wire
wire
out
out
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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