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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_rpc_reg.xml] - Diff between revs 134 and 135

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Rev 134	Rev 135
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`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`

`opencores.org`	`opencores.org`
`cde`	`cde`
`jtag`	`jtag`
`classic_rpc_reg default`	`classic_rpc_reg`


	`jtag`







	`test_logic_reset`
	`test_logic_reset`



	`capture_dr`
	`capture_dr`



	`shift_dr`
	`shift_dr`



	`update_dr_clk`
	`update_dr_clk`



`jtag`
	`tdi`
	`tdi`



`test_logic_reset`	`tdo`
`test_logic_reset`	`tdo`



`capture_dr`	`select`
`capture_dr`	`select`



`shift_dr`
`shift_dr`



`update_dr_clk`	`shiftcapture_dr_clk`
`update_dr_clk`	`shiftcapture_dr_clk`




`tdi`
`tdi`



`tdo`
`tdo`



`select`
`select`




`shiftcapture_dr_clk`
`shiftcapture_dr_clk`










	`update_value`







	`adhoc`


	`update_value`










	`capture_value`







	`adhoc`


	`capture_value`















`gen_verilog`
`104.0`
`none`
`common`
`./tools/verilog/gen_verilog`


`destination`
`jtag_classic_rpc_reg`












	`gen_verilog`
	`104.0`
	`none`
	`:common:`
	`tools/verilog/gen_verilog`


	`destination`
	`jtag_classic_rpc_reg`











`verilog`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="verilog"/>`






`commoncommon`
`Verilog`


`fs-common`








	`verilog`
	`verilog`
	`cde_jtag_classic_rpc_reg`


	`BITS`
	`16`


	`RESET_VALUE`
	`16'h0000`



	`fs-sim`





`sim:Simulation:`
`Verilog`


`fs-sim`




`syn:Synthesis:`
`Verilog`


`fs-syn`




	`rtl`
	`verilog:Kactus2:`
	`verilog`




`doc`	`verilog`


`spirit:library="Testbench"`	`ipxact:library="Testbench"`
`spirit:name="toolflow"`	`ipxact:name="toolflow"`
`spirit:version="documentation"/>`	`ipxact:version="verilog"/>`

`:Documentation:`
`Verilog`





	`common:common:`
	`Verilog`


	`fs-common`








	`sim:Simulation:`
	`Verilog`


	`fs-sim`




	`syn:Synthesis:`
	`Verilog`


	`fs-syn`







	`doc`


	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="documentation"/>`

	`:Documentation:`
	`Verilog`



`fs-common`



`../verilog/classic_rpc_reg`
`verilogSourcefragment`





`../verilog/copyright`
`verilogSourceinclude`







`fs-sim`




`../verilog/common/jtag_classic_rpc_reg`
`verilogSourcemodule`




`dest_dir`	`BITS16`
`../views/sim/`	`RESET_VALUE'h0`
`verilogSourcelibraryDir`






`fs-syn`



`../verilog/common/jtag_classic_rpc_reg`
`verilogSourcemodule`


	`capture_value`
	`wire`
	`in`
	`BITS-10`



`dest_dir`
`../views/syn/`
`verilogSourcelibraryDir`


	`update_value`
	`reg`
	`out`
	`BITS-10`





	`test_logic_reset`
	`wire`
	`in`





`fs-lint`

	`capture_dr`
	`wire`
`../verilog/common/jtag_classic_rpc_reg`	`in`
`verilogSourcemodule`




	`shift_dr`
`dest_dir../views/syn/`	`wire`
`verilogSourcelibraryDir`	`in`






	`shiftcapture_dr_clk`
	`wire`
	`in`






	`update_dr_clk`
`BITS16`	`wire`
`RESET_VALUE'h0`	`in`





	`tdi`
	`wire`
	`in`



	`tdo`
	`wire`
	`out`



	`select`
	`wire`
	`in`



`capture_value`
`wire`
`in`
`BITS-10`



`update_value`
`reg`
`out`
`BITS-10`

















	`fs-common`



	`../verilog/classic_rpc_reg`
	`verilogSourcefragment`





	`../verilog/copyright`
	`verilogSourceinclude`







	`fs-sim`




	`../verilog/common/jtag_classic_rpc_reg`
	`verilogSourcemodule`




	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`






	`fs-syn`



	`../verilog/common/jtag_classic_rpc_reg`
	`verilogSourcemodule`




	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`









	`fs-lint`



	`../verilog/common/jtag_classic_rpc_reg`
	`verilogSourcemodule`





	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_classic_rpc_reg.xml] - Diff between revs 134 and 135