URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Show entire file |
Details |
Blame |
View Log
| Rev 134 |
Rev 135 |
| Line 1... |
Line 1... |
|
|
|
|
|
|
-->
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
cde
|
cde
|
jtag
|
jtag
|
classic_sync default
|
classic_sync
|
|
|
|
|
|
|
|
|
|
|
jtag
|
jtag
|
|
|
|
|
|
|
|
|
|
|
|
|
test_logic_reset
|
|
test_logic_reset
|
|
|
|
|
|
|
|
capture_dr
|
|
capture_dr
|
|
|
|
|
|
|
|
shift_dr
|
|
shift_dr
|
|
|
|
|
|
|
|
update_dr_clk
|
test_logic_reset
|
update_dr_clk
|
test_logic_reset
|
|
|
|
|
|
|
|
capture_dr
|
|
capture_dr
|
|
|
|
|
|
|
tdi
|
shift_dr
|
tdi
|
shift_dr
|
|
|
|
|
|
|
tdo
|
update_dr_clk
|
tdo
|
update_dr_clk
|
|
|
|
|
|
|
|
|
|
|
select
|
|
select
|
|
|
|
|
|
|
|
|
tdi
|
|
tdi
|
|
|
|
|
|
|
shiftcapture_dr_clk
|
tdo
|
shiftcapture_dr_clk
|
tdo
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
select
|
|
select
|
|
|
|
|
|
|
|
|
|
|
|
|
|
shiftcapture_dr_clk
|
|
shiftcapture_dr_clk
|
|
|
syn_jtag
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
clk
|
|
syn_clk
|
|
|
|
|
|
|
|
|
|
test_logic_reset
|
|
syn_reset
|
|
|
|
|
|
|
|
capture_dr
|
|
syn_capture_dr
|
|
|
|
|
|
|
|
shift_dr
|
|
syn_shift_dr
|
|
|
|
|
|
|
|
update_dr
|
|
syn_update_dr
|
|
|
|
|
|
|
|
|
syn_jtag
|
tdi
|
|
syn_tdi_o
|
|
|
|
|
|
|
|
|
|
tdo
|
|
syn_tdo_i
|
|
|
|
|
|
|
|
|
|
|
|
select
|
|
syn_select
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
clk
|
|
syn_clk
|
|
|
|
|
|
|
|
|
|
|
|
test_logic_reset
|
|
syn_reset
|
|
|
|
|
|
|
|
capture_dr
|
|
syn_capture_dr
|
|
|
|
|
|
|
|
shift_dr
|
|
syn_shift_dr
|
|
|
|
|
|
|
gen_verilog
|
update_dr
|
104.0
|
syn_update_dr
|
none
|
|
common
|
|
./tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
jtag_classic_sync
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
tdi
|
|
syn_tdi_o
|
|
|
|
|
|
|
|
|
|
tdo
|
|
syn_tdo_i
|
|
|
|
|
|
|
|
|
|
|
|
select
|
|
syn_select
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
commoncommon
|
|
Verilog
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
Verilog
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
gen_verilog
|
|
104.0
|
|
none
|
|
:*common:*
|
|
tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
jtag_classic_sync
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
clk
|
|
wire
|
verilog
|
in
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="verilog"/>
|
|
|
|
|
|
|
|
|
syn_reset
|
|
reg
|
|
out
|
|
|
|
|
|
|
|
|
common:*common:*
|
|
Verilog
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
syn_shift_dr
|
|
reg
|
|
out
|
|
|
|
|
|
|
|
syn_capture_dr
|
|
reg
|
|
out
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
Verilog
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
syn_update_dr
|
|
reg
|
syn:*Synthesis:*
|
out
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
syn_tdi_o
|
|
reg
|
|
out
|
|
|
|
|
|
syn_select
|
|
reg
|
|
out
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
../verilog/classic_sync
|
|
verilogSourcefragment
|
|
|
|
|
|
|
clk
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
syn_reset
|
|
reg
|
|
out
|
|
|
|
|
|
|
|
syn_shift_dr
|
|
reg
|
|
out
|
|
|
|
|
|
|
|
syn_capture_dr
|
|
reg
|
|
out
|
|
|
|
|
|
|
|
syn_update_dr
|
fs-sim
|
reg
|
|
out
|
|
|
|
|
|
syn_tdi_o
|
|
reg
|
../verilog/copyright
|
out
|
verilogSourceinclude
|
|
|
|
|
|
|
syn_tdo_i
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
../verilog/common/jtag_classic_sync
|
|
verilogSourcemodule
|
|
|
|
|
|
|
syn_clk
|
|
wire
|
|
out
|
|
|
|
|
|
syn_select
|
dest_dir
|
reg
|
../views/sim/
|
out
|
verilogSource
|
|
libraryDir
|
|
|
|
|
|
|
|
|
|
|
test_logic_reset
|
|
wire
|
|
in
|
|
|
|
|
|
capture_dr
|
fs-syn
|
wire
|
|
in
|
|
|
|
|
|
shift_dr
|
|
wire
|
|
in
|
|
|
|
|
|
update_dr_clk
|
|
wire
|
../verilog/copyright
|
in
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
tdi
|
|
wire
|
../verilog/common/jtag_classic_sync
|
in
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
tdo
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
select
|
|
wire
|
|
in
|
|
|
|
|
|
shiftcapture_dr_clk
|
|
wire
|
|
in
|
|
|
|
|
|
|
dest_dir
|
|
../views/syn/
|
|
verilogSource
|
|
libraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-lint
|
|
|
|
dest_dir
|
|
../views/syn/
|
|
verilogSource
|
|
libraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
../verilog/classic_sync
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/common/jtag_classic_sync
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
dest_dir
|
|
../views/sim/
|
|
verilogSource
|
|
libraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/common/jtag_classic_sync
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
dest_dir
|
|
../views/syn/
|
|
verilogSource
|
|
libraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-lint
|
|
|
|
dest_dir
|
|
../views/syn/
|
|
verilogSource
|
|
libraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.