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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_tap.design.xml] - Diff between revs 134 and 135

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Rev 134	Rev 135
Line 1...	Line 1...



`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`

`opencores.org`	`opencores.org`
`cde`	`cde`
`jtag`	`jtag`
`tap.design`	`tap.design`





`tclk`
`wire`



`tclk_n`
`wire`





`tap_state`
`reg`	`jtag_clk`
`30`






`next_tap_state`
`reg`	`jtag_reset`
`30`





`shift_ir`
`reg`	`trst_n_pad_in`






`update_ir`
`reg`



`capture_ir`
`reg`


	`tdi_pad_in`








	`tdo_pad_out`




`next_tdo`
`reg`	`tdo_pad_oe`







`bypass_tdo`
`reg`




`chip_id_tdo`
`wire`


	`tms_pad_in`




`chip_id_select`
`wire`


	`chip_id_select`





`bypass_select`
`wire`	`chip_id_tdo`






	`capture_dr_o`







	`shift_dr_o`






`extest`
`wire`




	`tclk_pad_in`






`sample`
`wire`




`clamp`
`wire`


	`jtag_shift_clk`






`bsr_output_mode`
`reg`	`update_dr_clk_o`





`shiftcapture_dr`
`wire`	`jtag_clk`





	`shiftcapture_dr_o`





`aux_update_dr_o`
`wire`



`aux_jtag_clk`
`wire`





	`update_dr_o`








	`chip_id_value`







	`instruction`






`jtag_clk`






`trst_pad_in`	`bsr_output_mode`





`tdi_pad_in`





`chip_id_select`	`tap_highz_mode`





`chip_id_tdo`





`capture_dr_o`





`shift_dr_o`	`test_logic_reset_o`






	`next_tdo`






`tclk`







	`tdo_i`





	`aux_tdo_i`






	`bsr_select_o`





`jtag_shift_clk`	`chip_id_select`





	`extest`





`update_dr_clk_o`	`sample`






`jtag_clk`	`clamp`





`shiftcapture_dr`





`update_dr_o`	`select_o`






`chip_id_value`





	`aux_select_o`










	`shiftcapture_dr_clk_o`













	`aux_jtag_clk`





	`aux_update_dr_clk_o`





	`aux_shiftcapture_dr_clk_o`





	`aux_test_logic_reset_o`





	`aux_tdi_o`





	`aux_capture_dr_o`





	`aux_shift_dr_o`





	`aux_update_dr_o`





`clk_gater_jtag_shift_clk`	`tdi_o`





`clk_gater_jtag_update_clk`



`clk_gater_jtag_clk`





`chip_id_reg`

`32`
`CHIP_ID_VAL`
































	`tdi_pad`



	`tdi_pad_in`

	`tdi_pad_in`









	`tms_pad`



	`tms_pad_in`

	`tms_pad_in`









	`trst_n_pad`



	`trst_n_pad_in`

	`trst_n_pad_in`









	`tclk_pad`



	`tclk_pad_in`

	`tclk_pad_in`










	`tdo_pad`



	`tdo_pad_out`
	`tdo_pad_out`


	`tdo_pad_oe`
	`tdo_pad_oe`























	`clk_gater_jtag_shift_clk`



	`clk_gater_jtag_update_clk`



	`clk_gater_jtag_clk`





	`chip_id_reg`

	`32`
	`CHIP_ID_VAL`




	`cde_jtag_tap_logic`

	`INST_LENGTH`
	`INST_RETURN`
	`INST_RESET`
	`CHIP_ID_VAL`
	`NUM_USER`
	`EXTEST`
	`USER`
	`SAMPLE`
	`HIGHZ_MODE`
	`CHIP_ID_ACCESS`
	`CLAMP`
	`RPC_DATA`
	`RPC_ADD`
	`BYPASS`





	`cde_jtag_tap_sm`


	`INST_LENGTH`
	`INST_RETURN`
	`INST_RESET`
	`NUM_USER`
	`EXTEST`
	`USER`
	`SAMPLE`
	`HIGHZ_MODE`
	`CHIP_ID_ACCESS`
	`CLAMP`
	`RPC_DATA`
	`RPC_ADD`
	`BYPASS`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_tap.design.xml] - Diff between revs 134 and 135