URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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| Rev 134 |
Rev 135 |
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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cde
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cde
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jtag
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jtag
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tap default
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tap
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jtag
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test_logic_reset
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jtag
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test_logic_reset_o
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reg
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capture_dr
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capture_dr_o
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reg
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shift_dr
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shift_dr_o
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reg
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update_dr_clk
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test_logic_reset
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update_dr_clk_o
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test_logic_reset_o
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wire
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tdi
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capture_dr
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tdi_o
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capture_dr_o
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wire
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tdo
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shift_dr
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tdo_i
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shift_dr_o
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select
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update_dr_clk
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update_dr_clk_o
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select_o
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shiftcapture_dr_clk
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tdi
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tdi_o
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shiftcapture_dr_clk_o
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tdo
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tdo_i
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select
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select_o
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aux_jtag
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shiftcapture_dr_clk
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shiftcapture_dr_clk_o
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test_logic_reset
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aux_test_logic_reset_o
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wire
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capture_dr
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aux_capture_dr_o
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wire
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shift_dr
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aux_shift_dr_o
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wire
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update_dr_clk
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aux_update_dr_clk_o
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wire
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tdi
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aux_tdi_o
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wire
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tdo
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aux_tdo_i
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select
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aux_select_o
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shiftcapture_dr_clk
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aux_shiftcapture_dr_clk_o
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aux_jtag
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test_logic_reset
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aux_test_logic_reset_o
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capture_dr
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aux_capture_dr_o
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tclk_pad
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shift_dr
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aux_shift_dr_o
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pad_in
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tclk_pad_in
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update_dr_clk
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aux_update_dr_clk_o
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tdi
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aux_tdi_o
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tdi_pad
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tdo
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aux_tdo_i
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pad_in
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tdi_pad_in
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select
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aux_select_o
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shiftcapture_dr_clk
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aux_shiftcapture_dr_clk_o
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tms_pad
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pad_in
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tms_pad_in
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trst_n_pad
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pad_in
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trst_n_pad_in
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tdo_pad
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pad_out
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tdo_pad_out
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pad_oe
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tdo_pad_oe
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tclk_pad
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pad_in
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tclk_pad_in
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tdi_pad
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pad_in
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tdi_pad_in
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gen_verilog
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104.0
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none
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common
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./tools/verilog/gen_verilog
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destination
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jtag_tap
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tms_pad
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pad_in
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tms_pad_in
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trst_n_pad
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pad_in
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trst_n_pad_in
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Hierarchical
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spirit:library="cde"
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spirit:name="jtag"
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spirit:version="tap.design"/>
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verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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commoncommon
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Verilog
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fs-common
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tdo_pad
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-syn
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pad_out
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tdo_pad_out
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pad_oe
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tdo_pad_oe
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doc
|
|
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spirit:library="Testbench"
|
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spirit:name="toolflow"
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spirit:version="documentation"/>
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:*Documentation:*
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Verilog
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fs-common
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../verilog/tap
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verilogSourcefragment
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gen_verilog
|
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104.0
|
|
none
|
|
:*common:*
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tools/verilog/gen_verilog
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destination
|
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jtag_tap
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fs-sim
|
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../verilog/copyright
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verilogSourceinclude
|
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../verilog/common/jtag_tap
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verilogSourcemodule
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dest_dir
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../views/sim/
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verilogSourcelibraryDir
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fs-syn
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../verilog/SYNTHESYS
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verilogSourceinclude
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../verilog/copyright
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verilogSourceinclude
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../verilog/common/jtag_tap
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verilogSourcemodule
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dest_dir
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../views/syn/
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verilogSourcelibraryDir
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Hierarchical
|
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fs-lint
|
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dest_dir
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../views/syn/
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verilogSourcelibraryDir
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Hierarchical
|
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Hierarchical
|
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verilog
|
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ipxact:library="Testbench"
|
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ipxact:name="toolflow"
|
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ipxact:version="verilog"/>
|
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common:*common:*
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Verilog
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fs-common
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INST_LENGTH4
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INST_RETURN4'b1101
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INST_RESET4'b1111
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CHIP_ID_VAL32'h00000000
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NUM_USER2
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EXTEST4'b0000
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USER8'b1010_1001
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SAMPLE4'b0001
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HIGHZ_MODE4'b0010
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CHIP_ID_ACCESS4'b0011
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CLAMP4'b1000
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RPC_DATA4'b1010
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RPC_ADD4'b1001
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BYPASS4'b1111
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sim:*Simulation:*
|
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-syn
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tap_highz_mode
|
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reg
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doc
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out
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="documentation"/>
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|
:*Documentation:*
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Verilog
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bsr_output_mode
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reg
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out
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bsr_tdo_i
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wire
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in
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jtag_clk
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wire
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out
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update_dr_o
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reg
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out
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bsr_select_o
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wire
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out
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INST_LENGTH4
|
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INST_RETURN4'b1101
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INST_RESET4'b1111
|
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CHIP_ID_VAL32'h00000000
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NUM_USER2
|
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EXTEST4'b0000
|
|
USER8'b1010_1001
|
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SAMPLE4'b0001
|
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HIGHZ_MODE4'b0010
|
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CHIP_ID_ACCESS4'b0011
|
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CLAMP4'b1000
|
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RPC_DATA4'b1010
|
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RPC_ADD4'b1001
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BYPASS4'b1111
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tclk_pad_in
|
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wire
|
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in
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tdi_pad_in
|
|
wire
|
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in
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tms_pad_in
|
|
wire
|
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in
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trst_n_pad_in
|
|
wire
|
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in
|
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|
|
tdo_pad_out
|
|
wire
|
|
out
|
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|
|
|
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tdo_pad_oe
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
|
|
|
|
test_logic_reset_o
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
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|
capture_dr_o
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
shift_dr_o
|
|
wire
|
|
out
|
|
|
|
|
|
update_dr_clk_o
|
|
wire
|
|
out
|
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|
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|
|
tdi_o
|
|
wire
|
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out
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|
|
|
|
|
|
|
select_o
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
shiftcapture_dr_clk_o
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
tdo_i
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
|
aux_tdo_i
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
aux_test_logic_reset_o
|
|
wire
|
|
out
|
|
|
|
|
|
aux_capture_dr_o
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
aux_shift_dr_o
|
|
wire
|
|
out
|
|
|
|
|
|
aux_update_dr_clk_o
|
|
wire
|
|
out
|
|
|
|
|
|
aux_tdi_o
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
aux_select_o
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
aux_shiftcapture_dr_clk_o
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
tap_highz_mode
|
|
wire
|
|
out
|
|
|
|
|
|
bsr_output_mode
|
|
wire
|
|
out
|
|
|
|
|
|
bsr_tdo_i
|
|
wire
|
|
in
|
|
|
|
|
|
jtag_clk
|
|
wire
|
|
out
|
|
|
|
|
|
update_dr_o
|
|
wire
|
|
out
|
|
|
|
|
|
bsr_select_o
|
|
wire
|
|
out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/common/jtag_tap
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
dest_dir
|
|
../views/sim/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
|
|
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|
../verilog/SYNTHESIS
|
|
verilogSourceinclude
|
|
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|
|
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|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
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|
|
|
|
../verilog/common/jtag_tap
|
|
verilogSourcemodule
|
|
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|
dest_dir
|
|
../views/syn/
|
|
verilogSourcelibraryDir
|
|
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|
|
|
|
|
|
|
|
|
|
fs-lint
|
|
|
|
dest_dir
|
|
../views/syn/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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© copyright 1999-2024
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