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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [xml/] [cde_jtag_classic_sync_tb.xml] - Diff between revs 134 and 135

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Rev 134 Rev 135
Line 1... Line 1...
 
 
 
 
 
 
-->
-->
 
 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
 
opencores.org
opencores.org
cde
cde
jtag
jtag
classic_sync_tb
classic_sync_tb
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  gen_verilog
  gen_verilog
  104.0
  104.0
  none
  none
  common
  :*common:*
  ./tools/verilog/gen_verilog
  tools/verilog/gen_verilog
  
  
    
    
      destination
      destination
      jtag_classic_sync_tb
      jtag_classic_sync_tb
    
    
  
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
    JTAG_SEL8
    JTAG_SEL8
    JTAG_USER1_WIDTH8
    JTAG_USER1_WIDTH8
    JTAG_USER1_RESET8'h12
    JTAG_USER1_RESET8'h12
    JTAG_USER2_WIDTH24
    JTAG_USER2_WIDTH24
    JTAG_USER2_RESET24'h123456
    JTAG_USER2_RESET24'h123456
    JTAG_MODEL_DIVCNT     4'h4
    JTAG_MODEL_DIVCNT     4'h4
    JTAG_MODEL_SIZE       4
    JTAG_MODEL_SIZE       4
 
 
 
 
       
 
 
 
              
        
              Params
        
              
        Bfm
              
        
                                   spirit:library="cde"
        
                                   spirit:name="jtag"
        
                                   spirit:version="tap_dut.params"/>
 
             
 
              
 
 
 
 
 
              
 
              Bfm
 
              
 
                                   spirit:library="cde"
 
                                   spirit:name="jtag"
 
                                   spirit:version="classic_sync_bfm.design"/>
 
              
 
 
 
 
       
 
 
              
              
              icarus
              Params
              
              
              
              
                                   spirit:library="Testbench"
                                   ipxact:library="cde"
                                   spirit:name="toolflow"
                                   ipxact:name="jtag"
                                   spirit:version="icarus"/>
                                   ipxact:version="tap_dut.params"/>
              
             
              
              
 
 
 
 
 
              
 
                Bfm
 
                Bfm              
 
 
 
 
              
              
              commoncommon
              icarus
              Verilog
              
              
              
                     
                                   ipxact:library="Testbench"
                            fs-common
                                   ipxact:name="toolflow"
                     
                                   ipxact:version="icarus"/>
              
              
 
              
 
 
 
 
              
 
              sim:*Simulation:*
 
              Verilog
 
              
 
                     
 
                            fs-sim
 
                     
 
              
 
 
 
              
 
              lint:*Lint:*
 
              Verilog
 
              
 
                     
 
                            fs-lint
 
                     
 
              
 
 
 
      
              
 
              common:*common:*
 
              Verilog
 
              
 
                     
 
                            fs-common
 
                     
 
              
 
 
 
 
 
              
 
              sim:*Simulation:*
 
              Verilog
 
              
 
                     
 
                            fs-sim
 
                     
 
              
 
 
 
              
 
              lint:*Lint:*
 
              Verilog
 
              
 
                     
 
                            fs-lint
 
                     
 
              
 
 
 
      
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   
 
      fs-common
 
 
 
 
 
 
 
 
 
 
 
 
   
 
      fs-common
 
 
      
 
        
 
        ../verilog/tb.rpc_2
 
        verilogSource
 
        fragment
 
      
 
 
 
 
 
   
 
 
 
 
 
   
      
      fs-sim
        
 
        ../verilog/tb.rpc_2
 
        verilogSource
 
        fragment
 
      
 
 
 
 
 
   
 
 
 
 
 
   
 
      fs-sim
 
 
      
 
        
 
        ../verilog/common/jtag_classic_sync_tb
 
        verilogSourcemodule
 
      
 
 
 
 
 
   
 
 
 
 
 
   
      
      fs-lint
        
      
        ../verilog/common/jtag_classic_sync_tb
        
        verilogSourcemodule
        ../verilog/common/jtag_classic_sync_tb
      
        verilogSourcemodule
 
      
 
 
 
 
 
   
   
 
 
 
 
 
   
 
      fs-lint
 
      
 
        
 
        ../verilog/common/jtag_classic_sync_tb
 
        verilogSourcemodule
 
      
 
 
 
 
 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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