URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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cde
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cde
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jtag
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jtag
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tap_tb
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tap_tb
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gen_verilog
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gen_verilog
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104.0
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104.0
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none
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none
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common
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:*common:*
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./tools/verilog/gen_verilog
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tools/verilog/gen_verilog
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destination
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destination
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jtag_tap_tb
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jtag_tap_tb
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JTAG_SEL2
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JTAG_USER1_WIDTH8
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JTAG_USER1_RESET8'h12
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JTAG_USER2_WIDTH24
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JTAG_USER2_RESET24'h123456
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JTAG_MODEL_DIVCNT 4'h4
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JTAG_MODEL_SIZE 4
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INST_LENGTH4
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INST_RETURN4'b1101
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EXTEST4'b0000
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SAMPLE4'b0001
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HIGHZ_MODE4'b0010
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CHIP_ID_ACCESS4'b0011
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CLAMP4'b1000
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RPC_DATA4'b1010
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RPC_ADD4'b1001
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BYPASS4'b1111
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CHIP_ID_VAL32'h12345678
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Params
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spirit:library="cde"
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spirit:name="jtag"
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spirit:version="tap_dut.params"/>
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JTAG_SEL2
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Bfm
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JTAG_USER1_WIDTH8
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JTAG_USER1_RESET8'h12
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spirit:library="cde"
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JTAG_USER2_WIDTH24
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spirit:name="jtag"
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JTAG_USER2_RESET24'h123456
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spirit:version="bfm.design"/>
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JTAG_MODEL_DIVCNT 4'h4
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JTAG_MODEL_SIZE 4
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icarus
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="icarus"/>
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Bfm
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Dut
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commoncommon
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Verilog
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fs-common
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sim:*Simulation:*
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Verilog
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fs-sim
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lint:*Lint:*
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Verilog
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fs-lint
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Dut
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Dut
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Bfm
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Bfm
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icarus
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="icarus"/>
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common:*common:*
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Verilog
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fs-common
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fs-common
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sim:*Simulation:*
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Verilog
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fs-sim
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lint:*Lint:*
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Verilog
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fs-lint
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../verilog/tb.rpc_2
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verilogSource
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fragment
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fs-sim
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fs-common
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../verilog/common/jtag_tap_tb
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verilogSourcemodule
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fs-lint
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../verilog/tb.rpc_2
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verilogSource
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../verilog/common/jtag_tap_tb
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fragment
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verilogSourcemodule
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fs-sim
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../verilog/common/jtag_tap_tb
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verilogSourcemodule
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fs-lint
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../verilog/common/jtag_tap_tb
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verilogSourcemodule
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