OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [mult/] [rtl/] [xml/] [cde_mult_ord_r4.xml] - Diff between revs 134 and 135

Show entire file | Details | Blame | View Log

Rev 134 Rev 135
Line 1... Line 1...
 
 
 
 
 
 
-->
-->
 
 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
 
opencores.org
opencores.org
cde
cde
mult
mult
ord_r4  default
ord_r4
 
 
 
 
 
 
 
 
 
 
 
 
  gen_verilog
  gen_verilog
  104.0
  104.0
  none
  none
  common
  :*common:*
  ./tools/verilog/gen_verilog
  tools/verilog/gen_verilog
    
    
    
    
      destination
      destination
      mult_ord_r4
      mult_ord_r4
    
    
  
  
 
 
 
 
 
 
 
 
 
 
 
 
  gen_verilogLib_sim
  gen_verilogLib_sim
  105.0
  105.0
  none
  none
  :*Simulation:*
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
  tools/verilog/gen_verilogLib
    
    
    
    
      dest_dir
      dest_dir
      ../views
      ../views
    
    
    
    
      view
      view
      sim
      sim
    
    
  
  
 
 
 
 
 
 
 
 
  gen_verilogLib_syn
  gen_verilogLib_syn
  105.0
  105.0
  none
  none
  :*Synthesis:*
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
  tools/verilog/gen_verilogLib
    
    
    
    
      dest_dir
      dest_dir
      ../views
      ../views
    
    
    
    
      view
      view
      syn
      syn
    
    
  
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   
 
      fs-common
 
 
 
 
 
      
 
        ../verilog/top.ord_r4
 
        verilogSourcefragment
 
      
 
 
 
  
 
 
 
   
 
      fs-sim
 
 
 
      
        
        ../verilog/common/mult_ord_r4
 
        verilogSourcemodule
 
      
 
 
 
 
                        
 
                                verilog
 
                                verilog
 
                                cde_mult_ord_r4
 
                                
 
                                        
 
                                                WIDTH
 
                                                16
 
                                        
 
                                
 
                                
 
                                        fs-sim
 
                                
 
                        
 
                
 
 
      
 
        ../verilog/ord_r4.v
 
        verilogSourcemodule
 
      
 
 
 
 
 
 
 
      
       
        dest_dir../views/sim/
 
        verilogSourcelibraryDir
 
      
 
 
 
  
 
 
 
 
 
   
        
      fs-syn
        rtl
 
        verilog:Kactus2:
 
        verilog
 
        
 
 
      
 
        ../verilog/common/mult_ord_r4
 
        verilogSourcemodule
 
      
 
 
 
      
 
        ../verilog/ord_r4.v
 
        verilogSourcemodule
 
      
 
 
 
 
              
 
              common:*common:*
 
 
      
              Verilog
        dest_dir../views/syn/
              
        verilogSourcelibraryDir
                     
      
                            fs-common
 
                     
 
              
 
 
 
 
 
              
 
              sim:*Simulation:*
 
 
   
              Verilog
 
              
 
                     
 
                            fs-sim
 
                     
 
              
 
 
 
 
 
 
    
              
 
              syn:*Synthesis:*
 
 
      fs-lint
              Verilog
      
              
        dest_dir../views/syn/
                     
        verilogSourcelibraryDir
                            fs-syn
      
                     
 
              
 
 
    
 
 
 
 
              
 
              doc
 
              
 
              
 
                                   ipxact:library="Testbench"
 
                                   ipxact:name="toolflow"
 
                                   ipxact:version="documentation"/>
 
              
 
              :*Documentation:*
 
              Verilog
 
              
 
 
 
 
 
 
 
 
 
 
 
 
 
      
 
 
 
 
 
 
 
WIDTH16
 
 
 
 
 
 
 
 
 
 
 
 
       
 
 
 
              
 
              commoncommon
 
 
 
              Verilog
clk
              
wire
                     
in
                            fs-common
 
                     
 
              
 
 
 
 
reset
 
wire
 
in
 
 
 
 
              
 
              sim:*Simulation:*
 
 
 
              Verilog
 
              
 
                     
 
                            fs-sim
 
                     
 
              
 
 
 
 
 
 
 
              
 
              syn:*Synthesis:*
 
 
 
              Verilog
a_in
              
wire
                     
in
                            fs-syn
WIDTH-10
                     
 
              
 
 
 
 
 
              
b_in
              doc
wire
              
in
              
WIDTH-10
                                   spirit:library="Testbench"
 
                                   spirit:name="toolflow"
 
                                   spirit:version="documentation"/>
 
              
 
              :*Documentation:*
 
              Verilog
 
              
 
 
 
 
 
 
alu_op_mul
 
wire
 
in
 
 
 
 
 
 
 
ex_freeze
 
wire
 
in
 
 
 
 
      
 
 
 
 
 
 
 
 
mul_prod_r
 
reg
 
out
 
2*WIDTH-10
 
 
 
 
 
 
 
mul_stall
 
wire
 
out
 
 
 
 
clk
 
wire
 
in
 
 
 
 
 
reset
 
wire
 
in
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
a_in
 
wire
 
in
 
WIDTH-10
 
 
 
 
 
 
 
 
 
b_in
   
wire
      fs-common
in
 
WIDTH-10
 
 
 
 
 
 
 
alu_op_mul
      
wire
        ../verilog/top.ord_r4
in
        verilogSourcefragment
 
      
 
 
 
  
 
 
ex_freeze
   
wire
      fs-sim
in
 
 
 
 
 
 
      
 
        ../verilog/common/mult_ord_r4
 
        verilogSourcemodule
 
      
 
 
 
 
 
      
 
        ../verilog/ord_r4.v
 
        verilogSourcemodule
 
      
 
 
mul_prod_r
 
reg
 
out
 
2*WIDTH-10
 
 
 
 
 
 
 
mul_stall
      
wire
        dest_dir../views/sim/
out
        verilogSourcelibraryDir
 
      
 
 
 
  
 
 
 
 
 
   
 
      fs-syn
 
 
 
      
 
        ../verilog/common/mult_ord_r4
 
        verilogSourcemodule
 
      
 
 
 
      
 
        ../verilog/ord_r4.v
 
        verilogSourcemodule
 
      
 
 
 
 
 
      
 
        dest_dir../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
 
 
 
   
 
 
 
 
 
 
 
    
 
 
 
      fs-lint
 
      
 
        dest_dir../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
 
    
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.