URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Show entire file |
Details |
Blame |
View Log
| Rev 131 |
Rev 135 |
| Line 1... |
Line 1... |
|
|
|
|
|
|
-->
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
cde
|
cde
|
reset
|
reset
|
asyncdisable default
|
asyncdisable
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
fs-sim
|
|
|
|
|
|
|
dest_dir
|
dest_dir
|
../verilog/
|
../verilog/
|
verilogSourcelibraryDir
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
fs-syn
|
|
|
|
|
dest_dir
|
dest_dir
|
../verilog/
|
../verilog/
|
verilogSourcelibraryDir
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-lint
|
fs-lint
|
|
|
dest_dir
|
dest_dir
|
../verilog/
|
../verilog/
|
verilogSourcelibraryDir
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
|
|
Verilog
|
|
|
|
|
verilog
|
fs-sim
|
verilog
|
|
cde_reset_asyncdisable
|
|
|
|
|
|
WIDTH
|
|
1
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
rtl
|
|
verilog:Kactus2:
|
|
verilog
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
WIDTH1
|
|
|
|
|
|
|
|
|
|
reset_n
|
|
wire
|
doc
|
in
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
reset
|
|
wire
|
|
in
|
|
|
|
|
|
atg_asyncdisable
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
|
|
|
sync_reset
|
|
wire
|
|
in
|
|
WIDTH-10
|
|
|
|
|
|
|
|
reset_n_out
|
|
wire
|
WIDTH1
|
out
|
|
WIDTH-10
|
|
|
|
|
|
|
|
|
|
reset_out
|
reset_n
|
wire
|
wire
|
out
|
in
|
WIDTH-10
|
|
|
|
|
|
|
reset
|
|
wire
|
|
in
|
|
|
|
|
|
atg_asyncdisable
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
|
|
|
|
|
sync_reset
|
|
wire
|
|
in
|
|
WIDTH-10
|
|
|
|
|
|
|
|
reset_n_out
|
|
wire
|
|
out
|
|
WIDTH-10
|
|
|
|
|
|
|
|
reset_out
|
|
wire
|
|
out
|
|
WIDTH-10
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.