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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_word.xml] - Diff between revs 134 and 135

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Rev 134	Rev 135
Line 1...	Line 1...



`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`

`opencores.org`	`opencores.org`
`cde`	`cde`
`sram`	`sram`
`word default`	`word`





`slave_clk`	`slave_clk`





`clk`
`clk`





`mem`




	`clk`
	`clk`








`cs`
`cs`




`wr`
`wr`



	`mem`
`rd`
`rd`




`addr`
`addr`
`111`




	`cs`
	`cs`




`wdata`	`wr`
`wdata`	`wr`
`150`




	`rd`
	`rd`




`rdata`	`addr`
`rdata`	`addr`
`150`	`ADDR1`





	`wdata`
	`wdata`
	`150`




`be`
`be`
`10`




	`rdata`
	`rdata`
	`150`






	`be`
	`be`
	`10`




















	`gen_verilog`
	`104.0`
	`none`
	`:common:`
	`tools/verilog/gen_verilog`


	`destination`
	`sram_word`














`gen_verilog`
`104.0`
`none`
`common`
`./tools/verilog/gen_verilog`


`destination`
`sram_word`











	`verilog`
	`verilog`
	`cde_sram_word`


	`ADDR`
	`8`


	`WIDTH`
	`8`


	`WORDS`
	`256`


	`WRITETHRU`
	`1`



	`fs-sim`








`verilog`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="verilog"/>`




`commoncommon`
`Verilog`


`fs-common`






`sim:Simulation:`
`Verilog`


`fs-sim`




`syn:Synthesis:`
`Verilog`


`fs-syn`





`lintlint`
`Verilog`


`fs-lint`




	`rtl`
	`verilog:Kactus2:`
	`verilog`




	`verilog`


	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="verilog"/>`




	`common:common:`
	`Verilog`


	`fs-common`




`doc`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="documentation"/>`

`:Documentation:`
`Verilog`




	`sim:Simulation:`
	`Verilog`


	`fs-sim`




	`syn:Synthesis:`
	`Verilog`


	`fs-syn`






	`lint:Lint:`
	`Verilog`


	`fs-lint`








`cs`
`wire`	`doc`
`in`

	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="documentation"/>`

	`:Documentation:`
	`Verilog`


`addr`
`wire`
`in`
`ADDR1`



`wdata`
`wire`
`in`
`150`


`be`
`wire`
`in`
`10`


`rdata`
`reg`
`out`
`150`













	`clk`
	`wire`
	`in`


	`cs`
	`wire`
	`in`


	`wr`
	`wire`
	`in`


	`rd`
	`wire`
	`in`



`fs-common`



`../verilog/sram_word`
`verilogSourcefragment`


	`addr`
	`wire`
	`in`
	`ADDR1`





	`wdata`
	`wire`
	`in`
	`150`


	`be`
	`wire`
	`in`
	`10`


	`rdata`
`fs-sim`	`reg`
	`out`
	`150`





`../verilog/copyright`
`verilogSourceinclude`






`../verilog/common/sram_word`
`verilogSourcemodule`




`dest_dir../views/sim/`
`verilogSourcelibraryDir`








`fs-syn`



`../verilog/copyright`
`verilogSourceinclude`



	`fs-common`



	`../verilog/sram_word`
	`verilogSourcefragment`




`../verilog/common/sram_word`
`verilogSourcemodule`





`dest_dir../views/syn/`
`verilogSourcelibraryDir`






	`fs-sim`





	`../verilog/copyright`
	`verilogSourceinclude`




`fs-lint`
	`../verilog/common/sram_word`
	`verilogSourcemodule`




`dest_dir../views/syn/`	`dest_dir../views/sim/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`









	`fs-syn`



	`../verilog/copyright`
	`verilogSourceinclude`






	`../verilog/common/sram_word`
	`verilogSourcemodule`





	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`







`mem`
`8`

`mem`
`0x0000`

`mem`








	`fs-lint`



	`dest_dir../views/syn/`
	`verilogSourcelibraryDir`





















	`mem`
	`8`

	`mem`
	`0x0000`

	`mem`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_word.xml] - Diff between revs 134 and 135