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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_with_reset.xml] - Diff between revs 134 and 135

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Rev 134	Rev 135
Line 1...	Line 1...



`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://opencores.org"`	`xmlns:socgen="http://opencores.org"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`

`opencores.org`	`opencores.org`
`cde`	`cde`
`sync`	`sync`
`with_reset default`	`with_reset`





	`clk`






	`clk`
	`clk`








	`reset_n`






	`reset_n`
	`reset_n`









`gen_verilog`
`104.0`
`none`
`common`
`./tools/verilog/gen_verilog`


`destination`
`sync_with_reset`







	`data_in`






	`adhoc`
	`data_in`









	`data_out`






	`adhoc`
	`data_out`











`verilog`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="verilog"/>`











`commoncommon`
`Verilog`


`fs-common`






`sim:Simulation:`	`gen_verilog`
`Verilog`	`104.0`
	`none`
	`:common:`
`fs-sim`	`tools/verilog/gen_verilog`


	`destination`
	`sync_with_reset`





`syn:Synthesis:`
`Verilog`


`fs-syn`












`doc`


`spirit:library="Testbench"`
`spirit:name="toolflow"`
`spirit:version="documentation"/>`

`:Documentation:`
`Verilog`




	`verilog`
	`verilog`
	`cde_sync_with_reset`


	`WIDTH`
	`8`



	`fs-sim`










`WIDTH1`	`rtl`
`DEPTH2`	`verilog:Kactus2:`
	`verilog`



	`verilog`


	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="verilog"/>`



`clk`
`wire`
`in`


`reset_n`
`wire`
`in`



`data_in`
`wire`
`in`
`WIDTH-10`


`data_out`
`wire`
`out`
`WIDTH-10`



	`common:common:`
	`Verilog`


	`fs-common`






	`sim:Simulation:`
	`Verilog`


	`fs-sim`




	`syn:Synthesis:`
	`Verilog`


	`fs-syn`











`fs-common`	`doc`


	`ipxact:library="Testbench"`
	`ipxact:name="toolflow"`
	`ipxact:version="documentation"/>`

	`:Documentation:`
	`Verilog`




`../verilog/sync_with_reset`
`verilogSourcefragment`







	`WIDTH1`
	`DEPTH2`




	`clk`
	`wire`
	`in`


	`reset_n`
	`wire`
	`in`



`fs-sim`

	`data_in`
	`wire`
	`in`
	`WIDTH-10`


	`data_out`
	`wire`
`../verilog/copyright`	`out`
`verilogSourceinclude`	`WIDTH-10`





`../verilog/common/sync_with_reset`
`verilogSourcemodule`



`dest_dir`
`../views/sim/`
`verilogSource`
`libraryDir`







`fs-syn`



`../verilog/copyright`
`verilogSourceinclude`





`../verilog/common/sync_with_reset`
`verilogSourcemodule`




`dest_dir`
`../views/syn/`
`verilogSource`
`libraryDir`



	`fs-common`



	`../verilog/sync_with_reset`
	`verilogSourcefragment`






`fs-lint`


`dest_dir`
`../views/syn/`
`verilogSource`
`libraryDir`







	`fs-sim`





	`../verilog/copyright`
	`verilogSourceinclude`





	`../verilog/common/sync_with_reset`
	`verilogSourcemodule`



	`dest_dir`
	`../views/sim/`
	`verilogSource`
	`libraryDir`






	`fs-syn`



	`../verilog/copyright`
	`verilogSourceinclude`





	`../verilog/common/sync_with_reset`
	`verilogSourcemodule`




	`dest_dir`
	`../views/syn/`
	`verilogSource`
	`libraryDir`








	`fs-lint`


	`dest_dir`
	`../views/syn/`
	`verilogSource`
	`libraryDir`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sync/] [rtl/] [xml/] [cde_sync_with_reset.xml] - Diff between revs 134 and 135