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Line 1... |
Fitter report for spw_fifo_ulight
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Fitter report for spw_fifo_ulight
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Fri Sep 15 08:17:49 2017
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Mon Feb 5 00:57:17 2018
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Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition
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Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
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---------------------
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---------------------
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; Table of Contents ;
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; Table of Contents ;
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---------------------
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---------------------
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| Line 52... |
Line 52... |
functions, and any output files from any of the foregoing
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel MegaCore Function License Agreement, or other
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the Intel FPGA IP License Agreement, or other applicable license
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applicable license agreement, including, without limitation,
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agreement, including, without limitation, that your use is for
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that your use is for the sole purpose of programming logic
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the sole purpose of programming logic devices manufactured by
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devices manufactured by Intel and sold by Intel or its
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Intel and sold by Intel or its authorized distributors. Please
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authorized distributors. Please refer to the applicable
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refer to the applicable agreement for further details.
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agreement for further details.
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+-------------------------------------------------------------------------------+
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+----------------------------------------------------------------------------------------+
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; Fitter Summary ;
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; Fitter Summary ;
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+---------------------------------+---------------------------------------------+
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+---------------------------------+------------------------------------------------------+
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; Fitter Status ; Successful - Fri Sep 15 08:17:49 2017 ;
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; Fitter Status ; Successful - Mon Feb 5 00:57:17 2018 ;
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; Quartus Prime Version ; 17.0.1 Build 598 06/07/2017 SJ Lite Edition ;
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; Quartus Prime Version ; 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition ;
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; Revision Name ; spw_fifo_ulight ;
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; Revision Name ; spw_fifo_ulight ;
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; Top-level Entity Name ; SPW_ULIGHT_FIFO ;
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; Top-level Entity Name ; SPW_ULIGHT_FIFO ;
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; Family ; Cyclone V ;
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; Family ; Cyclone V ;
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; Device ; 5CSEMA4U23C6 ;
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; Device ; 5CSEMA4U23C6 ;
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; Timing Models ; Final ;
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; Timing Models ; Final ;
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; Logic utilization (in ALMs) ; 3,209 / 15,880 ( 20 % ) ;
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; Logic utilization (in ALMs) ; 3,362 / 15,880 ( 21 % ) ;
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; Total registers ; 4692 ;
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; Total registers ; 4633 ;
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; Total pins ; 19 / 314 ( 6 % ) ;
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; Total pins ; 19 / 314 ( 6 % ) ;
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; Total virtual pins ; 0 ;
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; Total virtual pins ; 0 ;
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; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ;
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; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ;
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; Total RAM Blocks ; 0 / 270 ( 0 % ) ;
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; Total RAM Blocks ; 0 / 270 ( 0 % ) ;
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; Total DSP Blocks ; 0 / 84 ( 0 % ) ;
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; Total DSP Blocks ; 0 / 84 ( 0 % ) ;
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| Line 84... |
Line 83... |
; Total HSSI PMA RX Deserializers ; 0 ;
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; Total HSSI PMA RX Deserializers ; 0 ;
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; Total HSSI TX PCSs ; 0 ;
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; Total HSSI TX PCSs ; 0 ;
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; Total HSSI PMA TX Serializers ; 0 ;
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; Total HSSI PMA TX Serializers ; 0 ;
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; Total PLLs ; 1 / 5 ( 20 % ) ;
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; Total PLLs ; 1 / 5 ( 20 % ) ;
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; Total DLLs ; 0 / 4 ( 0 % ) ;
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; Total DLLs ; 0 / 4 ( 0 % ) ;
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+---------------------------------+---------------------------------------------+
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+---------------------------------+------------------------------------------------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Fitter Settings ;
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; Fitter Settings ;
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+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
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+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
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| Line 96... |
Line 95... |
+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
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+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
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; Device ; 5CSEMA4U23C6 ; ;
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; Device ; 5CSEMA4U23C6 ; ;
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; Minimum Core Junction Temperature ; 0 ; ;
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; Minimum Core Junction Temperature ; 0 ; ;
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; Maximum Core Junction Temperature ; 85 ; ;
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; Maximum Core Junction Temperature ; 85 ; ;
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; Router Timing Optimization Level ; MAXIMUM ; Normal ;
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; Router Timing Optimization Level ; MAXIMUM ; Normal ;
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; Placement Effort Multiplier ; 90.0 ; 1.0 ;
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; Placement Effort Multiplier ; 4.0 ; 1.0 ;
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; PowerPlay Power Optimization During Fitting ; Extra effort ; Normal compilation ;
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; Auto RAM to MLAB Conversion ; Off ; On ;
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; Optimize IOC Register Placement for Timing ; Off ; Normal ;
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; Power Optimization During Fitting ; Extra effort ; Normal compilation ;
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; Fitter Initial Placement Seed ; 893763639 ; 1 ;
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; Optimize IOC Register Placement for Timing ; Pack All IO Registers ; Normal ;
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; Auto Delay Chains ; Off ; On ;
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; Auto Delay Chains for High Fanout Input Pins ; On ; Off ;
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; Perform Physical Synthesis for Combinational Logic for Fitting ; On ; Off ;
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; Perform Physical Synthesis for Combinational Logic for Performance ; On ; Off ;
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; Perform Asynchronous Signal Pipelining ; On ; Off ;
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; Physical Synthesis Effort Level ; Extra ; Normal ;
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; Physical Synthesis Effort Level ; Extra ; Normal ;
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; Logic Cell Insertion - Logic Duplication ; Off ; Auto ;
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; Logic Cell Insertion - Logic Duplication ; Off ; Auto ;
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; Auto Register Duplication ; Off ; Auto ;
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; Auto Register Duplication ; Off ; Auto ;
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; Optimize Design for Metastability ; Off ; On ;
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; Use smart compilation ; Off ; Off ;
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
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; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Enable compact report table ; Off ; Off ;
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; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
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; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
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; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
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; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
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; Optimize Hold Timing ; All Paths ; All Paths ;
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; Optimize Hold Timing ; All Paths ; All Paths ;
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; Optimize Multi-Corner Timing ; On ; On ;
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; Optimize Multi-Corner Timing ; On ; On ;
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; Auto RAM to MLAB Conversion ; On ; On ;
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; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
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; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
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; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
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; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
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; SSN Optimization ; Off ; Off ;
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; SSN Optimization ; Off ; Off ;
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; Optimize Timing ; Normal compilation ; Normal compilation ;
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; Optimize Timing ; Normal compilation ; Normal compilation ;
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; Optimize Timing for ECOs ; Off ; Off ;
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; Optimize Timing for ECOs ; Off ; Off ;
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; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
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; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
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; Final Placement Optimizations ; Automatically ; Automatically ;
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; Final Placement Optimizations ; Automatically ; Automatically ;
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; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
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; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
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; Fitter Initial Placement Seed ; 1 ; 1 ;
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; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
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; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
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; Weak Pull-Up Resistor ; Off ; Off ;
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; Weak Pull-Up Resistor ; Off ; Off ;
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; Enable Bus-Hold Circuitry ; Off ; Off ;
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; Enable Bus-Hold Circuitry ; Off ; Off ;
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; Auto Packed Registers ; Auto ; Auto ;
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; Auto Packed Registers ; Auto ; Auto ;
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; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
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; Auto Delay Chains ; On ; On ;
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; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
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; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
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; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
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; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
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; Perform Register Duplication for Performance ; Off ; Off ;
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; Perform Register Duplication for Performance ; Off ; Off ;
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; Perform Register Retiming for Performance ; Off ; Off ;
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; Perform Register Retiming for Performance ; Off ; Off ;
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; Perform Asynchronous Signal Pipelining ; Off ; Off ;
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; Fitter Effort ; Auto Fit ; Auto Fit ;
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; Fitter Effort ; Auto Fit ; Auto Fit ;
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; Auto Global Clock ; On ; On ;
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; Auto Global Clock ; On ; On ;
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; Auto Global Register Control Signals ; On ; On ;
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; Auto Global Register Control Signals ; On ; On ;
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; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
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; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
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; Synchronizer Identification ; Auto ; Auto ;
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; Synchronizer Identification ; Auto ; Auto ;
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; Enable Beneficial Skew Optimization ; On ; On ;
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; Enable Beneficial Skew Optimization ; On ; On ;
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; Optimize Design for Metastability ; On ; On ;
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; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
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; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
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; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
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; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
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; Clamping Diode ; Off ; Off ;
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; Clamping Diode ; Off ; Off ;
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; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
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; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
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; Advanced Physical Optimization ; On ; On ;
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; Advanced Physical Optimization ; On ; On ;
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| Line 154... |
Line 153... |
; Processors ; Number ;
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; Processors ; Number ;
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+----------------------------+-------------+
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+----------------------------+-------------+
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; Number detected on machine ; 4 ;
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; Number detected on machine ; 4 ;
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; Maximum allowed ; 2 ;
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; Maximum allowed ; 2 ;
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; ; ;
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; ; ;
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; Average used ; 1.02 ;
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; Average used ; 1.09 ;
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; Maximum used ; 2 ;
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; Maximum used ; 2 ;
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; ; ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processor 1 ; 100.0% ;
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; Processor 2 ; 2.2% ;
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; Processor 2 ; 9.1% ;
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+----------------------------+-------------+
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+----------------------------+-------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Fitter Netlist Optimizations ;
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; Fitter Netlist Optimizations ;
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+--------------------------------------------------------------------------------------------------------------------------------------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------+
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; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
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; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
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+--------------------------------------------------------------------------------------------------------------------------------------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------+
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; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
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; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
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; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
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; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
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; FPGA_CLK1_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
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; FPGA_CLK1_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
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; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add0~41 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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+--------------------------------------------------------------------------------------------------------------------------------------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add0~42 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add1~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~1_RESYN160_BDD161 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_RESYN126_BDD127 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_RESYN148_BDD149 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_RESYN150_BDD151 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_RESYN152_BDD153 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0_RESYN138_BDD139 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0_RESYN140_BDD141 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~21 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~23 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~53 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~54 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~55 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~56 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~66 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~97 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~97_RESYN164_BDD165 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~98 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~98_RESYN166_BDD167 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~99 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~100 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~100_RESYN168_BDD169 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; debounce_db:db_system_spwulight_b|Add0~62 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; debounce_db:db_system_spwulight_b|counter~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; detector_tokens:m_x|always5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; detector_tokens:m_x|always5~1_RESYN162_BDD163 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; detector_tokens:m_x|always5~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; detector_tokens:m_x|counter_neg:cnt_neg|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; detector_tokens:m_x|counter_neg:cnt_neg|Selector3~0_RESYN26_BDD27 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~1_RESYN170_BDD171 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add0~42 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add5~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add7~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Selector18~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|rd_ptr~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add0~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add1~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add2~26 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1_RESYN48_BDD49 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2_RESYN50_BDD51 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3_RESYN52_BDD53 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4_RESYN54_BDD55 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5_RESYN56_BDD57 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6_RESYN58_BDD59 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7_RESYN60_BDD61 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8_RESYN62_BDD63 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9_RESYN64_BDD65 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10_RESYN66_BDD67 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11_RESYN68_BDD69 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12_RESYN70_BDD71 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after850ns~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|always2~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13_RESYN72_BDD73 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector3~0_RESYN24_BDD25 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~1_RESYN104_BDD105 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy|always0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy|always0~1_RESYN154_BDD155 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always0~1_RESYN156_BDD157 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always1~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always1~0_RESYN158_BDD159 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Equal4~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Selector7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Selector7~1_RESYN128_BDD129 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|ShiftRight1~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|char_sent~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|char_sent~4_RESYN146_BDD147 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~1_RESYN10_BDD11 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~14 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~15 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16_RESYN4_BDD5 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16_RESYN6_BDD7 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~7 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~8 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9_RESYN0_BDD1 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9_RESYN2_BDD3 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~18 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~18_RESYN130_BDD131 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~21 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~21_RESYN40_BDD41 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23_RESYN132_BDD133 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23_RESYN134_BDD135 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~25 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~25_RESYN136_BDD137 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~28 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~1_RESYN12_BDD13 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~1_RESYN120_BDD121 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~3_RESYN122_BDD123 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~4_RESYN124_BDD125 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|Selector15~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|Selector15~1_RESYN142_BDD143 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~0_RESYN144_BDD145 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~3_RESYN76_BDD77 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~5_RESYN78_BDD79 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p~10_RESYN80_BDD81 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.000~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~9_RESYN98_BDD99 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~10_RESYN100_BDD101 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~11 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12_RESYN108_BDD109 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12_RESYN110_BDD111 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~13 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~13_RESYN112_BDD113 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~14_RESYN114_BDD115 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~0_RESYN14_BDD15 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
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|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~0_RESYN16_BDD17 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~2_RESYN18_BDD19 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~3_RESYN84_BDD85 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~4 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~5_RESYN20_BDD21 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0]~_Duplicate_1 ; Q ; ;
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[0]~output ; I ; ;
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1]~_Duplicate_1 ; Q ; ;
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[1]~output ; I ; ;
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2]~_Duplicate_1 ; Q ; ;
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[2]~output ; I ; ;
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3]~_Duplicate_1 ; Q ; ;
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[3]~output ; I ; ;
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4]~_Duplicate_1 ; Q ; ;
|
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[4]~output ; I ; ;
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------+
|
|
|
|
|
+---------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------+
|
; Ignored Assignments ;
|
; Ignored Assignments ;
|
+--------------+-----------------+--------------+------------+---------------+----------------+
|
+--------------+-----------------+--------------+------------+---------------+----------------+
|
| Line 185... |
Line 366... |
; I/O Standard ; SPW_ULIGHT_FIFO ; ; KEY ; 3.3-V LVTTL ; QSF Assignment ;
|
; I/O Standard ; SPW_ULIGHT_FIFO ; ; KEY ; 3.3-V LVTTL ; QSF Assignment ;
|
; I/O Standard ; SPW_ULIGHT_FIFO ; ; LED ; 3.3-V LVTTL ; QSF Assignment ;
|
; I/O Standard ; SPW_ULIGHT_FIFO ; ; LED ; 3.3-V LVTTL ; QSF Assignment ;
|
+--------------+-----------------+--------------+------------+---------------+----------------+
|
+--------------+-----------------+--------------+------------+---------------+----------------+
|
|
|
|
|
+---------------------------------------------------------------------------------------------------+
|
+----------------------------------------------------------------------------------------------------+
|
; Incremental Compilation Preservation Summary ;
|
; Incremental Compilation Preservation Summary ;
|
+---------------------+---------------------+----------------------------+--------------------------+
|
+---------------------+----------------------+----------------------------+--------------------------+
|
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
|
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
|
+---------------------+---------------------+----------------------------+--------------------------+
|
+---------------------+----------------------+----------------------------+--------------------------+
|
; Placement (by node) ; ; ; ;
|
; Placement (by node) ; ; ; ;
|
; -- Requested ; 0.00 % ( 0 / 9969 ) ; 0.00 % ( 0 / 9969 ) ; 0.00 % ( 0 / 9969 ) ;
|
; -- Requested ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ;
|
; -- Achieved ; 0.00 % ( 0 / 9969 ) ; 0.00 % ( 0 / 9969 ) ; 0.00 % ( 0 / 9969 ) ;
|
; -- Achieved ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Routing (by net) ; ; ; ;
|
; Routing (by net) ; ; ; ;
|
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
|
+---------------------+---------------------+----------------------------+--------------------------+
|
+---------------------+----------------------+----------------------------+--------------------------+
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Incremental Compilation Partition Settings ;
|
; Incremental Compilation Partition Settings ;
|
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
|
+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
|
| Line 215... |
Line 396... |
+------------------------------------------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------------------------------+
|
; Incremental Compilation Placement Preservation ;
|
; Incremental Compilation Placement Preservation ;
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
|
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
; Top ; 0.00 % ( 0 / 9951 ) ; N/A ; Source File ; N/A ; ;
|
; Top ; 0.00 % ( 0 / 10065 ) ; N/A ; Source File ; N/A ; ;
|
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 18 ) ; N/A ; Source File ; N/A ; ;
|
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 18 ) ; N/A ; Source File ; N/A ; ;
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
|
|
|
|
|
+--------------+
|
+--------------+
|
| Line 231... |
Line 412... |
+---------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------+
|
; Fitter Resource Usage Summary ;
|
; Fitter Resource Usage Summary ;
|
+-------------------------------------------------------------+-----------------------+-------+
|
+-------------------------------------------------------------+-----------------------+-------+
|
; Resource ; Usage ; % ;
|
; Resource ; Usage ; % ;
|
+-------------------------------------------------------------+-----------------------+-------+
|
+-------------------------------------------------------------+-----------------------+-------+
|
; Logic utilization (ALMs needed / total ALMs on device) ; 3,209 / 15,880 ; 20 % ;
|
; Logic utilization (ALMs needed / total ALMs on device) ; 3,362 / 15,880 ; 21 % ;
|
; ALMs needed [=A-B+C] ; 3,209 ; ;
|
; ALMs needed [=A-B+C] ; 3,362 ; ;
|
; [A] ALMs used in final placement [=a+b+c+d] ; 3,800 / 15,880 ; 24 % ;
|
; [A] ALMs used in final placement [=a+b+c+d] ; 3,835 / 15,880 ; 24 % ;
|
; [a] ALMs used for LUT logic and registers ; 1,607 ; ;
|
; [a] ALMs used for LUT logic and registers ; 1,626 ; ;
|
; [b] ALMs used for LUT logic ; 1,468 ; ;
|
; [b] ALMs used for LUT logic ; 1,539 ; ;
|
; [c] ALMs used for registers ; 725 ; ;
|
; [c] ALMs used for registers ; 670 ; ;
|
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
|
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
|
; [B] Estimate of ALMs recoverable by dense packing ; 601 / 15,880 ; 4 % ;
|
; [B] Estimate of ALMs recoverable by dense packing ; 489 / 15,880 ; 3 % ;
|
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 10 / 15,880 ; < 1 % ;
|
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 16 / 15,880 ; < 1 % ;
|
; [a] Due to location constrained logic ; 0 ; ;
|
; [a] Due to location constrained logic ; 0 ; ;
|
; [b] Due to LAB-wide signal conflicts ; 5 ; ;
|
; [b] Due to LAB-wide signal conflicts ; 10 ; ;
|
; [c] Due to LAB input limits ; 5 ; ;
|
; [c] Due to LAB input limits ; 6 ; ;
|
; [d] Due to virtual I/Os ; 0 ; ;
|
; [d] Due to virtual I/Os ; 0 ; ;
|
; ; ; ;
|
; ; ; ;
|
; Difficulty packing design ; Low ; ;
|
; Difficulty packing design ; Low ; ;
|
; ; ; ;
|
; ; ; ;
|
; Total LABs: partially or completely used ; 455 / 1,588 ; 29 % ;
|
; Total LABs: partially or completely used ; 464 / 1,588 ; 29 % ;
|
; -- Logic LABs ; 455 ; ;
|
; -- Logic LABs ; 464 ; ;
|
; -- Memory LABs (up to half of total LABs) ; 0 ; ;
|
; -- Memory LABs (up to half of total LABs) ; 0 ; ;
|
; ; ; ;
|
; ; ; ;
|
; Combinational ALUT usage for logic ; 5,301 ; ;
|
; Combinational ALUT usage for logic ; 5,522 ; ;
|
; -- 7 input functions ; 59 ; ;
|
; -- 7 input functions ; 72 ; ;
|
; -- 6 input functions ; 1,198 ; ;
|
; -- 6 input functions ; 1,329 ; ;
|
; -- 5 input functions ; 825 ; ;
|
; -- 5 input functions ; 874 ; ;
|
; -- 4 input functions ; 1,419 ; ;
|
; -- 4 input functions ; 1,532 ; ;
|
; -- <=3 input functions ; 1,800 ; ;
|
; -- <=3 input functions ; 1,715 ; ;
|
; Combinational ALUT usage for route-throughs ; 473 ; ;
|
; Combinational ALUT usage for route-throughs ; 415 ; ;
|
; ; ; ;
|
; ; ; ;
|
; Dedicated logic registers ; 4,692 ; ;
|
; Dedicated logic registers ; 4,628 ; ;
|
; -- By type: ; ; ;
|
; -- By type: ; ; ;
|
; -- Primary logic registers ; 4,664 / 31,760 ; 15 % ;
|
; -- Primary logic registers ; 4,592 / 31,760 ; 14 % ;
|
; -- Secondary logic registers ; 28 / 31,760 ; < 1 % ;
|
; -- Secondary logic registers ; 36 / 31,760 ; < 1 % ;
|
; -- By function: ; ; ;
|
; -- By function: ; ; ;
|
; -- Design implementation registers ; 4,692 ; ;
|
; -- Design implementation registers ; 4,628 ; ;
|
; -- Routing optimization registers ; 0 ; ;
|
; -- Routing optimization registers ; 0 ; ;
|
; ; ; ;
|
; ; ; ;
|
; Virtual pins ; 0 ; ;
|
; Virtual pins ; 0 ; ;
|
; I/O pins ; 19 / 314 ; 6 % ;
|
; I/O pins ; 19 / 314 ; 6 % ;
|
; -- Clock pins ; 2 / 6 ; 33 % ;
|
; -- Clock pins ; 2 / 6 ; 33 % ;
|
; -- Dedicated input pins ; 0 / 21 ; 0 % ;
|
; -- Dedicated input pins ; 0 / 21 ; 0 % ;
|
|
; I/O registers ; 5 ; ;
|
; ; ; ;
|
; ; ; ;
|
; Hard processor system peripheral utilization ; ; ;
|
; Hard processor system peripheral utilization ; ; ;
|
; -- Boot from FPGA ; 1 / 1 ( 100 % ) ; ;
|
; -- Boot from FPGA ; 1 / 1 ( 100 % ) ; ;
|
; -- Clock resets ; 1 / 1 ( 100 % ) ; ;
|
; -- Clock resets ; 1 / 1 ( 100 % ) ; ;
|
; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
|
; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
|
| Line 308... |
Line 490... |
; ; ; ;
|
; ; ; ;
|
; Total DSP Blocks ; 0 / 84 ; 0 % ;
|
; Total DSP Blocks ; 0 / 84 ; 0 % ;
|
; ; ; ;
|
; ; ; ;
|
; Fractional PLLs ; 1 / 5 ; 20 % ;
|
; Fractional PLLs ; 1 / 5 ; 20 % ;
|
; Global signals ; 4 ; ;
|
; Global signals ; 4 ; ;
|
; -- Global clocks ; 4 / 16 ; 25 % ;
|
; -- Global clocks ; 3 / 16 ; 19 % ;
|
; -- Quadrant clocks ; 0 / 72 ; 0 % ;
|
; -- Quadrant clocks ; 0 / 72 ; 0 % ;
|
; -- Horizontal periphery clocks ; 0 / 12 ; 0 % ;
|
; -- Horizontal periphery clocks ; 0 / 12 ; 0 % ;
|
; SERDES Transmitters ; 0 / 76 ; 0 % ;
|
; SERDES Transmitters ; 0 / 76 ; 0 % ;
|
; SERDES Receivers ; 0 / 76 ; 0 % ;
|
; SERDES Receivers ; 0 / 76 ; 0 % ;
|
; JTAGs ; 0 / 1 ; 0 % ;
|
; JTAGs ; 0 / 1 ; 0 % ;
|
| Line 320... |
Line 502... |
; CRC blocks ; 0 / 1 ; 0 % ;
|
; CRC blocks ; 0 / 1 ; 0 % ;
|
; Remote update blocks ; 0 / 1 ; 0 % ;
|
; Remote update blocks ; 0 / 1 ; 0 % ;
|
; Oscillator blocks ; 0 / 1 ; 0 % ;
|
; Oscillator blocks ; 0 / 1 ; 0 % ;
|
; Impedance control blocks ; 0 / 3 ; 0 % ;
|
; Impedance control blocks ; 0 / 3 ; 0 % ;
|
; Hard Memory Controllers ; 0 / 2 ; 0 % ;
|
; Hard Memory Controllers ; 0 / 2 ; 0 % ;
|
; Average interconnect usage (total/H/V) ; 4.9% / 5.0% / 4.6% ; ;
|
; Average interconnect usage (total/H/V) ; 6.0% / 6.2% / 5.2% ; ;
|
; Peak interconnect usage (total/H/V) ; 19.3% / 19.7% / 19.5% ; ;
|
; Peak interconnect usage (total/H/V) ; 26.6% / 28.9% / 23.3% ; ;
|
; Maximum fan-out ; 3124 ; ;
|
; Maximum fan-out ; 3073 ; ;
|
; Highest non-global fan-out ; 1270 ; ;
|
; Highest non-global fan-out ; 2974 ; ;
|
; Total fan-out ; 39487 ; ;
|
; Total fan-out ; 40291 ; ;
|
; Average fan-out ; 3.76 ; ;
|
; Average fan-out ; 3.79 ; ;
|
+-------------------------------------------------------------+-----------------------+-------+
|
+-------------------------------------------------------------+-----------------------+-------+
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Fitter Partition Statistics ;
|
; Fitter Partition Statistics ;
|
+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+
|
+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+
|
; Statistic ; Top ; ulight_fifo_hps_0_hps_io_border:border ; hard_block:auto_generated_inst ;
|
; Statistic ; Top ; ulight_fifo_hps_0_hps_io_border:border ; hard_block:auto_generated_inst ;
|
+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+
|
+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+
|
; Logic utilization (ALMs needed / total ALMs on device) ; 3209 / 15880 ( 20 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; Logic utilization (ALMs needed / total ALMs on device) ; 3362 / 15880 ( 21 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; ALMs needed [=A-B+C] ; 3209 ; 0 ; 0 ;
|
; ALMs needed [=A-B+C] ; 3362 ; 0 ; 0 ;
|
; [A] ALMs used in final placement [=a+b+c+d] ; 3800 / 15880 ( 24 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; [A] ALMs used in final placement [=a+b+c+d] ; 3835 / 15880 ( 24 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; [a] ALMs used for LUT logic and registers ; 1607 ; 0 ; 0 ;
|
; [a] ALMs used for LUT logic and registers ; 1626 ; 0 ; 0 ;
|
; [b] ALMs used for LUT logic ; 1468 ; 0 ; 0 ;
|
; [b] ALMs used for LUT logic ; 1539 ; 0 ; 0 ;
|
; [c] ALMs used for registers ; 725 ; 0 ; 0 ;
|
; [c] ALMs used for registers ; 670 ; 0 ; 0 ;
|
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; 0 ;
|
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; 0 ;
|
; [B] Estimate of ALMs recoverable by dense packing ; 601 / 15880 ( 4 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; [B] Estimate of ALMs recoverable by dense packing ; 489 / 15880 ( 3 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 10 / 15880 ( < 1 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 16 / 15880 ( < 1 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;
|
; [a] Due to location constrained logic ; 0 ; 0 ; 0 ;
|
; [a] Due to location constrained logic ; 0 ; 0 ; 0 ;
|
; [b] Due to LAB-wide signal conflicts ; 5 ; 0 ; 0 ;
|
; [b] Due to LAB-wide signal conflicts ; 10 ; 0 ; 0 ;
|
; [c] Due to LAB input limits ; 5 ; 0 ; 0 ;
|
; [c] Due to LAB input limits ; 6 ; 0 ; 0 ;
|
; [d] Due to virtual I/Os ; 0 ; 0 ; 0 ;
|
; [d] Due to virtual I/Os ; 0 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Difficulty packing design ; Low ; Low ; Low ;
|
; Difficulty packing design ; Low ; Low ; Low ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Total LABs: partially or completely used ; 455 / 1588 ( 29 % ) ; 0 / 1588 ( 0 % ) ; 0 / 1588 ( 0 % ) ;
|
; Total LABs: partially or completely used ; 464 / 1588 ( 29 % ) ; 0 / 1588 ( 0 % ) ; 0 / 1588 ( 0 % ) ;
|
; -- Logic LABs ; 455 ; 0 ; 0 ;
|
; -- Logic LABs ; 464 ; 0 ; 0 ;
|
; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; 0 ;
|
; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Combinational ALUT usage for logic ; 5301 ; 0 ; 0 ;
|
; Combinational ALUT usage for logic ; 5522 ; 0 ; 0 ;
|
; -- 7 input functions ; 59 ; 0 ; 0 ;
|
; -- 7 input functions ; 72 ; 0 ; 0 ;
|
; -- 6 input functions ; 1198 ; 0 ; 0 ;
|
; -- 6 input functions ; 1329 ; 0 ; 0 ;
|
; -- 5 input functions ; 825 ; 0 ; 0 ;
|
; -- 5 input functions ; 874 ; 0 ; 0 ;
|
; -- 4 input functions ; 1419 ; 0 ; 0 ;
|
; -- 4 input functions ; 1532 ; 0 ; 0 ;
|
; -- <=3 input functions ; 1800 ; 0 ; 0 ;
|
; -- <=3 input functions ; 1715 ; 0 ; 0 ;
|
; Combinational ALUT usage for route-throughs ; 473 ; 0 ; 0 ;
|
; Combinational ALUT usage for route-throughs ; 415 ; 0 ; 0 ;
|
; Memory ALUT usage ; 0 ; 0 ; 0 ;
|
; Memory ALUT usage ; 0 ; 0 ; 0 ;
|
; -- 64-address deep ; 0 ; 0 ; 0 ;
|
; -- 64-address deep ; 0 ; 0 ; 0 ;
|
; -- 32-address deep ; 0 ; 0 ; 0 ;
|
; -- 32-address deep ; 0 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Dedicated logic registers ; 0 ; 0 ; 0 ;
|
; Dedicated logic registers ; 0 ; 0 ; 0 ;
|
; -- By type: ; ; ; ;
|
; -- By type: ; ; ; ;
|
; -- Primary logic registers ; 4664 / 31760 ( 15 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ;
|
; -- Primary logic registers ; 4592 / 31760 ( 14 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ;
|
; -- Secondary logic registers ; 28 / 31760 ( < 1 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ;
|
; -- Secondary logic registers ; 36 / 31760 ( < 1 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ;
|
; -- By function: ; ; ; ;
|
; -- By function: ; ; ; ;
|
; -- Design implementation registers ; 4692 ; 0 ; 0 ;
|
; -- Design implementation registers ; 4628 ; 0 ; 0 ;
|
; -- Routing optimization registers ; 0 ; 0 ; 0 ;
|
; -- Routing optimization registers ; 0 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Virtual pins ; 0 ; 0 ; 0 ;
|
; Virtual pins ; 0 ; 0 ; 0 ;
|
; I/O pins ; 17 ; 0 ; 2 ;
|
; I/O pins ; 17 ; 0 ; 2 ;
|
; I/O registers ; 0 ; 0 ; 0 ;
|
; I/O registers ; 5 ; 0 ; 0 ;
|
; Total block memory bits ; 0 ; 0 ; 0 ;
|
; Total block memory bits ; 0 ; 0 ; 0 ;
|
; Total block memory implementation bits ; 0 ; 0 ; 0 ;
|
; Total block memory implementation bits ; 0 ; 0 ; 0 ;
|
; Clock enable block ; 1 / 110 ( < 1 % ) ; 0 / 110 ( 0 % ) ; 3 / 110 ( 2 % ) ;
|
; Clock enable block ; 0 / 110 ( 0 % ) ; 0 / 110 ( 0 % ) ; 3 / 110 ( 2 % ) ;
|
|
; Double data rate I/O output circuitry ; 5 / 304 ( 1 % ) ; 0 / 304 ( 0 % ) ; 0 / 304 ( 0 % ) ;
|
; HPS DBG APB interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
; HPS DBG APB interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
; Fractional PLL ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
; Fractional PLL ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
; HPS boot from FPGA interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
; HPS boot from FPGA interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
; HPS clock resets interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
; HPS clock resets interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
; FPGA-to-HPS interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
; FPGA-to-HPS interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
|
| Line 393... |
Line 576... |
; PLL Output Counter ; 0 / 45 ( 0 % ) ; 0 / 45 ( 0 % ) ; 1 / 45 ( 2 % ) ;
|
; PLL Output Counter ; 0 / 45 ( 0 % ) ; 0 / 45 ( 0 % ) ; 1 / 45 ( 2 % ) ;
|
; PLL Reconfiguration Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
; PLL Reconfiguration Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
; PLL Reference Clock Select Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
; PLL Reference Clock Select Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Connections ; ; ; ;
|
; Connections ; ; ; ;
|
; -- Input Connections ; 4319 ; 0 ; 45 ;
|
; -- Input Connections ; 4377 ; 0 ; 40 ;
|
; -- Registered Input Connections ; 3150 ; 0 ; 0 ;
|
; -- Registered Input Connections ; 3099 ; 0 ; 0 ;
|
; -- Output Connections ; 45 ; 0 ; 4319 ;
|
; -- Output Connections ; 40 ; 0 ; 4377 ;
|
; -- Registered Output Connections ; 1 ; 0 ; 0 ;
|
; -- Registered Output Connections ; 1 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Internal Connections ; ; ; ;
|
; Internal Connections ; ; ; ;
|
; -- Total Connections ; 39862 ; 0 ; 4401 ;
|
; -- Total Connections ; 40728 ; 0 ; 4454 ;
|
; -- Registered Connections ; 19902 ; 0 ; 0 ;
|
; -- Registered Connections ; 23593 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; External Connections ; ; ; ;
|
; External Connections ; ; ; ;
|
; -- Top ; 0 ; 0 ; 4364 ;
|
; -- Top ; 0 ; 0 ; 4417 ;
|
; -- ulight_fifo_hps_0_hps_io_border:border ; 0 ; 0 ; 0 ;
|
; -- ulight_fifo_hps_0_hps_io_border:border ; 0 ; 0 ; 0 ;
|
; -- hard_block:auto_generated_inst ; 4364 ; 0 ; 0 ;
|
; -- hard_block:auto_generated_inst ; 4417 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Partition Interface ; ; ; ;
|
; Partition Interface ; ; ; ;
|
; -- Input Ports ; 5 ; 0 ; 46 ;
|
; -- Input Ports ; 5 ; 0 ; 41 ;
|
; -- Output Ports ; 10 ; 0 ; 106 ;
|
; -- Output Ports ; 10 ; 0 ; 106 ;
|
; -- Bidir Ports ; 0 ; 0 ; 0 ;
|
; -- Bidir Ports ; 0 ; 0 ; 0 ;
|
; ; ; ; ;
|
; ; ; ; ;
|
; Registered Ports ; ; ; ;
|
; Registered Ports ; ; ; ;
|
; -- Registered Input Ports ; 0 ; 0 ; 0 ;
|
; -- Registered Input Ports ; 0 ; 0 ; 0 ;
|
| Line 433... |
Line 616... |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Input Pins ;
|
; Input Pins ;
|
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
|
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
|
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
; FPGA_CLK1_50 ; Y13 ; 4A ; 38 ; 0 ; 0 ; 3125 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
|
; FPGA_CLK1_50 ; Y13 ; 4A ; 38 ; 0 ; 0 ; 3074 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
|
; KEY[0] ; AH17 ; 4A ; 46 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
|
; KEY[0] ; AH17 ; 4A ; 46 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
|
; KEY[1] ; AH16 ; 4A ; 46 ; 0 ; 51 ; 20 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
|
; KEY[1] ; AH16 ; 4A ; 46 ; 0 ; 51 ; 18 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ;
|
; din_a ; Y15 ; 4A ; 46 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;
|
; din_a ; Y15 ; 4A ; 46 ; 0 ; 0 ; 21 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;
|
; din_a(n) ; AA15 ; 4A ; 46 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;
|
; din_a(n) ; AA15 ; 4A ; 46 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;
|
; sin_a ; AE20 ; 4A ; 51 ; 0 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;
|
; sin_a ; AE20 ; 4A ; 51 ; 0 ; 0 ; 16 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;
|
; sin_a(n) ; AD20 ; 4A ; 51 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;
|
; sin_a(n) ; AD20 ; 4A ; 51 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ;
|
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Output Pins ;
|
; Output Pins ;
|
+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
|
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
|
+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
|
; LED[0] ; W15 ; 5A ; 68 ; 12 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[0] ; W15 ; 5A ; 68 ; 12 ; 20 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[1] ; AA24 ; 5A ; 68 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[1] ; AA24 ; 5A ; 68 ; 13 ; 37 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[2] ; V16 ; 5A ; 68 ; 13 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[2] ; V16 ; 5A ; 68 ; 13 ; 3 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[3] ; V15 ; 5A ; 68 ; 13 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[3] ; V15 ; 5A ; 68 ; 13 ; 20 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[4] ; AF26 ; 5A ; 68 ; 10 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[4] ; AF26 ; 5A ; 68 ; 10 ; 77 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[5] ; AE26 ; 5A ; 68 ; 10 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[5] ; AE26 ; 5A ; 68 ; 10 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[6] ; Y16 ; 5A ; 68 ; 12 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[6] ; Y16 ; 5A ; 68 ; 12 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[7] ; AA23 ; 5A ; 68 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; LED[7] ; AA23 ; 5A ; 68 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ;
|
; dout_a ; AG28 ; 4A ; 65 ; 0 ; 34 ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 1 ; 0 ; Off ; User ; - ; - ;
|
; dout_a ; AG28 ; 4A ; 65 ; 0 ; 34 ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 1 ; 0 ; Off ; User ; - ; - ;
|
; dout_a(n) ; AH27 ; 4A ; 65 ; 0 ; 51 ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 1 ; 0 ; Off ; User ; - ; - ;
|
; dout_a(n) ; AH27 ; 4A ; 65 ; 0 ; 51 ; no ; no ; no ; no ; no ; no ; no ; Off ; LVDS ; Default ; Off ; -- ; 1 ; 1 ; 0 ; Off ; User ; - ; - ;
|
| Line 1188... |
Line 1371... |
; ; ;
|
; ; ;
|
+--------------------------------------------------------------------------------------------------------------------------------------+----------------------------+
|
+--------------------------------------------------------------------------------------------------------------------------------------+----------------------------+
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll ; ;
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll ; ;
|
; -- PLL Type ; Integer PLL ;
|
; -- PLL Type ; Integer PLL ;
|
; -- PLL Location ; FRACTIONALPLL_X68_Y1_N0 ;
|
; -- PLL Location ; FRACTIONALPLL_X68_Y1_N0 ;
|
; -- PLL Feedback clock type ; none ;
|
; -- PLL Feedback clock type ; Global Clock ;
|
; -- PLL Bandwidth ; Auto ;
|
; -- PLL Bandwidth ; Auto ;
|
; -- PLL Bandwidth Range ; 2100000 to 1400000 Hz ;
|
; -- PLL Bandwidth Range ; 1200000 to 600000 Hz ;
|
; -- Reference Clock Frequency ; 100.0 MHz ;
|
; -- Reference Clock Frequency ; 50.0 MHz ;
|
; -- Reference Clock Sourced by ; Dedicated Pin ;
|
; -- Reference Clock Sourced by ; Dedicated Pin ;
|
; -- PLL VCO Frequency ; 400.0 MHz ;
|
; -- PLL VCO Frequency ; 400.0 MHz ;
|
; -- PLL Operation Mode ; Direct ;
|
; -- PLL Operation Mode ; Normal ;
|
; -- PLL Freq Min Lock ; 75.000000 MHz ;
|
; -- PLL Freq Min Lock ; 37.500000 MHz ;
|
; -- PLL Freq Max Lock ; 200.000000 MHz ;
|
; -- PLL Freq Max Lock ; 100.000000 MHz ;
|
; -- PLL Enable ; On ;
|
; -- PLL Enable ; On ;
|
; -- PLL Fractional Division ; N/A ;
|
; -- PLL Fractional Division ; N/A ;
|
; -- M Counter ; 8 ;
|
; -- M Counter ; 16 ;
|
; -- N Counter ; 2 ;
|
; -- N Counter ; 2 ;
|
; -- PLL Refclk Select ; ;
|
; -- PLL Refclk Select ; ;
|
; -- PLL Refclk Select Location ; PLLREFCLKSELECT_X68_Y7_N0 ;
|
; -- PLL Refclk Select Location ; PLLREFCLKSELECT_X68_Y7_N0 ;
|
; -- PLL Reference Clock Input 0 source ; clk_0 ;
|
; -- PLL Reference Clock Input 0 source ; clk_0 ;
|
; -- PLL Reference Clock Input 1 source ; clk_1 ;
|
; -- PLL Reference Clock Input 1 source ; clk_1 ;
|
| Line 1233... |
Line 1416... |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Fitter Resource Utilization by Entity ;
|
; Fitter Resource Utilization by Entity ;
|
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
; |SPW_ULIGHT_FIFO ; 3209.0 (0.5) ; 3800.0 (0.5) ; 601.0 (0.0) ; 10.0 (0.0) ; 0.0 (0.0) ; 5301 (1) ; 4692 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 19 ; 0 ; |SPW_ULIGHT_FIFO ; SPW_ULIGHT_FIFO ; work ;
|
; |SPW_ULIGHT_FIFO ; 3361.5 (0.5) ; 3835.0 (0.5) ; 488.5 (0.0) ; 15.0 (0.0) ; 0.0 (0.0) ; 5522 (1) ; 4628 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 19 ; 0 ; |SPW_ULIGHT_FIFO ; SPW_ULIGHT_FIFO ; work ;
|
; |clock_reduce:R_400_to_2_5_10_100_200_300MHZ| ; 44.5 (44.5) ; 46.3 (46.3) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 76 (76) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ ; clock_reduce ; work ;
|
; |clock_reduce:R_400_to_2_5_10_100_200_300MHZ| ; 109.5 (109.5) ; 117.7 (117.7) ; 9.2 (9.2) ; 1.0 (1.0) ; 0.0 (0.0) ; 184 (184) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ ; clock_reduce ; work ;
|
; |debounce_db:db_system_spwulight_b| ; 19.0 (19.0) ; 19.0 (19.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 38 (38) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b ; debounce_db ; work ;
|
; |debounce_db:db_system_spwulight_b| ; 18.5 (18.5) ; 19.5 (19.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 37 (37) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b ; debounce_db ; work ;
|
; |detector_tokens:m_x| ; 35.7 (35.7) ; 67.8 (67.8) ; 32.2 (32.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 59 (59) ; 106 (106) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x ; detector_tokens ; work ;
|
; |detector_tokens:m_x| ; 18.8 (9.2) ; 22.5 (10.3) ; 3.7 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 30 (18) ; 38 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x ; detector_tokens ; work ;
|
; |spw_ulight_con_top_x:A_SPW_TOP| ; 764.9 (0.3) ; 1126.5 (0.5) ; 365.1 (0.2) ; 3.5 (0.0) ; 0.0 (0.0) ; 984 (1) ; 1439 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP ; spw_ulight_con_top_x ; work ;
|
; |bit_capture_control:capture_c| ; 0.7 (0.7) ; 1.0 (1.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_control:capture_c ; bit_capture_control ; work ;
|
; |fifo_rx:rx_data| ; 272.4 (272.4) ; 435.3 (435.3) ; 164.4 (164.4) ; 1.5 (1.5) ; 0.0 (0.0) ; 318 (318) ; 615 (615) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data ; fifo_rx ; work ;
|
; |bit_capture_data:capture_d| ; 1.7 (1.7) ; 2.8 (2.8) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_data:capture_d ; bit_capture_data ; work ;
|
; |fifo_tx:tx_data| ; 256.6 (256.6) ; 417.8 (417.8) ; 163.3 (163.3) ; 2.0 (2.0) ; 0.0 (0.0) ; 297 (297) ; 608 (608) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ; fifo_tx ; work ;
|
; |counter_neg:cnt_neg| ; 7.3 (7.3) ; 8.3 (8.3) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|counter_neg:cnt_neg ; counter_neg ; work ;
|
; |top_spw_ultra_light:SPW| ; 235.6 (0.0) ; 272.8 (0.0) ; 37.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 368 (0) ; 216 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW ; top_spw_ultra_light ; work ;
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; |spw_ulight_con_top_x:A_SPW_TOP| ; 839.8 (0.2) ; 1146.0 (0.5) ; 315.8 (0.2) ; 9.5 (0.0) ; 0.0 (0.0) ; 1060 (1) ; 1499 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP ; spw_ulight_con_top_x ; work ;
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; |FSM_SPW:FSM| ; 70.3 (70.3) ; 73.4 (73.4) ; 3.1 (3.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 125 (125) ; 47 (47) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM ; FSM_SPW ; work ;
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; |fifo_rx:rx_data| ; 291.7 (50.6) ; 440.5 (58.3) ; 150.3 (7.7) ; 1.5 (0.0) ; 0.0 (0.0) ; 340 (87) ; 633 (48) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data ; fifo_rx ; work ;
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; |RX_SPW:RX| ; 41.9 (41.9) ; 64.4 (64.4) ; 22.5 (22.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 68 (68) ; 109 (109) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX ; RX_SPW ; work ;
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; |mem_data:mem_dta_fifo_tx| ; 241.1 (241.1) ; 382.2 (382.2) ; 142.6 (142.6) ; 1.5 (1.5) ; 0.0 (0.0) ; 253 (253) ; 585 (585) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx ; mem_data ; work ;
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; |TX_SPW:TX| ; 123.3 (123.3) ; 135.0 (135.0) ; 11.7 (11.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 175 (175) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX ; TX_SPW ; work ;
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; |fifo_tx:tx_data| ; 287.5 (31.0) ; 418.8 (32.3) ; 139.3 (1.3) ; 8.0 (0.0) ; 0.0 (0.0) ; 299 (46) ; 627 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ; fifo_tx ; work ;
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; |ulight_fifo:u0| ; 2344.4 (0.0) ; 2539.8 (0.0) ; 201.9 (0.0) ; 6.5 (0.0) ; 0.0 (0.0) ; 4143 (0) ; 3105 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0 ; ulight_fifo ; ulight_fifo ;
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; |mem_data:mem_dta_fifo_tx| ; 256.5 (256.5) ; 386.6 (386.6) ; 138.1 (138.1) ; 8.0 (8.0) ; 0.0 (0.0) ; 253 (253) ; 585 (585) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx ; mem_data ; work ;
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; |top_spw_ultra_light:SPW| ; 260.3 (0.0) ; 286.2 (0.0) ; 25.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 420 (0) ; 239 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW ; top_spw_ultra_light ; work ;
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; |FSM_SPW:FSM| ; 75.6 (75.6) ; 78.3 (78.3) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 130 (130) ; 59 (59) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM ; FSM_SPW ; work ;
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; |RX_SPW:RX| ; 41.0 (0.3) ; 50.5 (1.5) ; 9.5 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 66 (3) ; 75 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX ; RX_SPW ; work ;
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; |bit_capture_control:capture_c| ; 0.9 (0.9) ; 1.1 (1.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c ; bit_capture_control ; work ;
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; |bit_capture_data:capture_d| ; 2.6 (2.6) ; 3.2 (3.2) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d ; bit_capture_data ; work ;
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; |counter_neg:cnt_neg| ; 7.5 (7.5) ; 8.1 (8.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg ; counter_neg ; work ;
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; |rx_buffer_fsm:buffer_fsm| ; 1.3 (1.3) ; 1.5 (1.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_buffer_fsm:buffer_fsm ; rx_buffer_fsm ; work ;
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; |rx_control_data_rdy:control_data_rdy| ; 3.0 (3.0) ; 3.7 (3.7) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy ; rx_control_data_rdy ; work ;
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; |rx_data_buffer_data_w:buffer_data_flag| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_buffer_data_w:buffer_data_flag ; rx_data_buffer_data_w ; work ;
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; |rx_data_control_p:data_control| ; 10.6 (10.6) ; 10.7 (10.7) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (11) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control ; rx_data_control_p ; work ;
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; |rx_data_receive:rx_dtarcv| ; 13.7 (13.7) ; 19.8 (19.8) ; 6.1 (6.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (28) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv ; rx_data_receive ; work ;
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; |TX_SPW:TX| ; 143.8 (0.0) ; 157.3 (0.0) ; 13.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 224 (0) ; 105 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX ; TX_SPW ; work ;
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; |tx_data_send:tx_data_snd| ; 23.3 (23.3) ; 23.3 (23.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 30 (30) ; 29 (29) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd ; tx_data_send ; work ;
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; |tx_fsm_m:tx_fsm| ; 120.1 (81.2) ; 134.0 (91.8) ; 13.9 (10.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 194 (132) ; 76 (43) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm ; tx_fsm_m ; work ;
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; |tx_fct_counter:tx_fct_cnt| ; 25.1 (25.1) ; 26.7 (26.7) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 42 (42) ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt ; tx_fct_counter ; work ;
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; |tx_fct_send:tx_fct_snd| ; 13.8 (13.8) ; 15.5 (15.5) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 20 (20) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd ; tx_fct_send ; work ;
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; |ulight_fifo:u0| ; 2374.4 (0.0) ; 2528.8 (0.0) ; 158.9 (0.0) ; 4.5 (0.0) ; 0.0 (0.0) ; 4210 (0) ; 3049 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0 ; ulight_fifo ; ulight_fifo ;
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; |altera_reset_controller:rst_controller| ; 0.0 (0.0) ; 1.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller ; altera_reset_controller ; ulight_fifo ;
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; |altera_reset_controller:rst_controller| ; 0.0 (0.0) ; 1.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller ; altera_reset_controller ; ulight_fifo ;
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; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.0 (0.0) ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ;
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; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.0 (0.0) ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ;
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; |altera_reset_controller:rst_controller_001| ; 0.7 (0.0) ; 1.3 (0.0) ; 0.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001 ; altera_reset_controller ; ulight_fifo ;
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; |altera_reset_controller:rst_controller_001| ; 0.7 (0.0) ; 1.5 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001 ; altera_reset_controller ; ulight_fifo ;
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; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.7 (0.7) ; 1.3 (1.3) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ;
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; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.7 (0.7) ; 1.5 (1.5) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ;
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; |ulight_fifo_auto_start:auto_start| ; 0.7 (0.7) ; 1.0 (1.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:auto_start ; ulight_fifo_auto_start ; ulight_fifo ;
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; |ulight_fifo_auto_start:auto_start| ; 0.6 (0.6) ; 1.0 (1.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:auto_start ; ulight_fifo_auto_start ; ulight_fifo ;
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; |ulight_fifo_auto_start:data_read_en_rx| ; 0.9 (0.9) ; 1.1 (1.1) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx ; ulight_fifo_auto_start ; ulight_fifo ;
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; |ulight_fifo_auto_start:data_read_en_rx| ; 0.8 (0.8) ; 1.3 (1.3) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx ; ulight_fifo_auto_start ; ulight_fifo ;
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; |ulight_fifo_auto_start:link_disable| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_disable ; ulight_fifo_auto_start ; ulight_fifo ;
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; |ulight_fifo_auto_start:link_disable| ; 1.2 (1.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_disable ; ulight_fifo_auto_start ; ulight_fifo ;
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; |ulight_fifo_auto_start:link_start| ; 0.9 (0.9) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_start ; ulight_fifo_auto_start ; ulight_fifo ;
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; |ulight_fifo_auto_start:link_start| ; 0.6 (0.6) ; 1.0 (1.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_start ; ulight_fifo_auto_start ; ulight_fifo ;
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; |ulight_fifo_auto_start:timecode_tx_enable| ; 1.0 (1.0) ; 1.1 (1.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable ; ulight_fifo_auto_start ; ulight_fifo ;
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; |ulight_fifo_auto_start:timecode_tx_enable| ; 1.2 (1.2) ; 1.4 (1.4) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable ; ulight_fifo_auto_start ; ulight_fifo ;
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; |ulight_fifo_auto_start:write_en_tx| ; 0.7 (0.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx ; ulight_fifo_auto_start ; ulight_fifo ;
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; |ulight_fifo_auto_start:write_en_tx| ; 1.3 (1.3) ; 1.4 (1.4) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx ; ulight_fifo_auto_start ; ulight_fifo ;
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; |ulight_fifo_clock_sel:clock_sel| ; 2.1 (2.1) ; 2.6 (2.6) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel ; ulight_fifo_clock_sel ; ulight_fifo ;
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; |ulight_fifo_clock_sel:clock_sel| ; 2.1 (2.1) ; 2.2 (2.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel ; ulight_fifo_clock_sel ; ulight_fifo ;
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; |ulight_fifo_counter_rx_fifo:counter_rx_fifo| ; 3.0 (3.0) ; 3.1 (3.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
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; |ulight_fifo_counter_rx_fifo:counter_rx_fifo| ; 2.5 (2.5) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
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; |ulight_fifo_counter_rx_fifo:counter_tx_fifo| ; 2.7 (2.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
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; |ulight_fifo_counter_rx_fifo:counter_tx_fifo| ; 2.6 (2.6) ; 3.0 (3.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
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; |ulight_fifo_counter_rx_fifo:fsm_info| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
|
; |ulight_fifo_counter_rx_fifo:fsm_info| ; 2.3 (2.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info ; ulight_fifo_counter_rx_fifo ; ulight_fifo ;
|
; |ulight_fifo_data_flag_rx:data_flag_rx| ; 5.2 (5.2) ; 5.2 (5.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx ; ulight_fifo_data_flag_rx ; ulight_fifo ;
|
; |ulight_fifo_data_flag_rx:data_flag_rx| ; 4.1 (4.1) ; 4.1 (4.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx ; ulight_fifo_data_flag_rx ; ulight_fifo ;
|
; |ulight_fifo_data_info:data_info| ; 7.1 (7.1) ; 7.1 (7.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info ; ulight_fifo_data_info ; ulight_fifo ;
|
; |ulight_fifo_data_info:data_info| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info ; ulight_fifo_data_info ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status| ; 0.7 (0.7) ; 0.8 (0.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:timecode_ready_rx| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:timecode_ready_rx| ; 0.3 (0.3) ; 0.5 (0.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:timecode_tx_ready| ; 0.4 (0.4) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_fifo_empty_rx_status:timecode_tx_ready| ; 0.5 (0.5) ; 0.7 (0.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ;
|
; |ulight_fifo_hps_0:hps_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0 ; ulight_fifo_hps_0 ; ulight_fifo ;
|
; |ulight_fifo_hps_0:hps_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0 ; ulight_fifo_hps_0 ; ulight_fifo ;
|
; |ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces ; ulight_fifo_hps_0_fpga_interfaces ; ulight_fifo ;
|
; |ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces ; ulight_fifo_hps_0_fpga_interfaces ; ulight_fifo ;
|
; |ulight_fifo_led_pio_test:led_pio_test| ; 2.2 (2.2) ; 3.9 (3.9) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test ; ulight_fifo_led_pio_test ; ulight_fifo ;
|
; |ulight_fifo_led_pio_test:led_pio_test| ; 2.9 (2.9) ; 4.2 (4.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test ; ulight_fifo_led_pio_test ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0:mm_interconnect_0| ; 2300.2 (0.0) ; 2484.3 (0.0) ; 190.6 (0.0) ; 6.5 (0.0) ; 0.0 (0.0) ; 4046 (0) ; 3014 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0 ; ulight_fifo_mm_interconnect_0 ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0:mm_interconnect_0| ; 2337.0 (0.0) ; 2478.1 (0.0) ; 145.6 (0.0) ; 4.5 (0.0) ; 0.0 (0.0) ; 4124 (0) ; 2969 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0 ; ulight_fifo_mm_interconnect_0 ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.3 (3.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo| ; 18.6 (18.6) ; 21.8 (21.8) ; 3.3 (3.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo| ; 20.1 (20.1) ; 21.0 (21.0) ; 1.2 (1.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo| ; 4.5 (4.5) ; 4.8 (4.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo| ; 4.3 (4.3) ; 4.3 (4.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo| ; 18.9 (18.9) ; 20.0 (20.0) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo| ; 20.2 (20.2) ; 20.2 (20.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo| ; 5.4 (5.4) ; 5.4 (5.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo| ; 6.4 (6.4) ; 6.7 (6.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo| ; 14.3 (14.3) ; 21.0 (21.0) ; 6.8 (6.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo| ; 14.7 (14.7) ; 17.7 (17.7) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo| ; 6.0 (6.0) ; 6.0 (6.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo| ; 6.1 (6.1) ; 6.2 (6.2) ; 0.2 (0.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo| ; 17.5 (17.5) ; 17.1 (17.1) ; 0.0 (0.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo| ; 17.0 (17.0) ; 18.2 (18.2) ; 1.3 (1.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo| ; 8.9 (8.9) ; 8.9 (8.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo| ; 9.0 (9.0) ; 9.0 (9.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo| ; 19.3 (19.3) ; 19.2 (19.2) ; 0.0 (0.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo| ; 18.3 (18.3) ; 18.5 (18.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo| ; 13.7 (13.7) ; 13.8 (13.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 19 (19) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo| ; 4.2 (4.2) ; 4.2 (4.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo| ; 14.0 (14.0) ; 21.8 (21.8) ; 7.8 (7.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo| ; 15.1 (15.1) ; 20.6 (20.6) ; 5.6 (5.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo| ; 19.4 (19.4) ; 20.3 (20.3) ; 1.3 (1.3) ; 0.4 (0.4) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo| ; 20.7 (20.7) ; 22.0 (22.0) ; 1.5 (1.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo| ; 2.3 (2.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo| ; 2.7 (2.7) ; 2.8 (2.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo| ; 17.1 (17.1) ; 17.9 (17.9) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo| ; 17.2 (17.2) ; 18.8 (18.8) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo| ; 2.4 (2.4) ; 2.8 (2.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo| ; 2.6 (2.6) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo| ; 17.6 (17.6) ; 17.6 (17.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo| ; 18.2 (18.2) ; 19.7 (19.7) ; 1.8 (1.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo| ; 2.7 (2.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo| ; 2.6 (2.6) ; 2.8 (2.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo| ; 18.2 (18.2) ; 18.6 (18.6) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo| ; 18.7 (18.7) ; 19.3 (19.3) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo| ; 2.8 (2.8) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo| ; 2.3 (2.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo| ; 14.3 (14.3) ; 19.0 (19.0) ; 4.7 (4.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo| ; 14.4 (14.4) ; 17.5 (17.5) ; 3.1 (3.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo| ; 5.5 (5.5) ; 5.5 (5.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo| ; 5.2 (5.2) ; 6.3 (6.3) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo| ; 17.8 (17.8) ; 17.8 (17.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo| ; 17.7 (17.7) ; 19.0 (19.0) ; 1.5 (1.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo| ; 5.7 (5.7) ; 5.7 (5.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo| ; 6.0 (6.0) ; 6.2 (6.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo| ; 16.6 (16.6) ; 23.4 (23.4) ; 6.8 (6.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo| ; 21.0 (21.0) ; 21.6 (21.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo| ; 2.8 (2.8) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo| ; 20.1 (20.1) ; 21.0 (21.0) ; 1.9 (1.9) ; 1.0 (1.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo| ; 19.5 (19.5) ; 20.1 (20.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo| ; 2.7 (2.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo| ; 16.2 (16.2) ; 23.3 (23.3) ; 7.0 (7.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo| ; 20.8 (20.8) ; 22.2 (22.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo| ; 2.7 (2.7) ; 3.3 (3.3) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo| ; 2.4 (2.4) ; 2.4 (2.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
|
; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo| ; 17.5 (17.5) ; 17.7 (17.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo| ; 17.0 (17.0) ; 17.0 (17.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo| ; 6.9 (6.9) ; 6.9 (6.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo| ; 7.5 (7.5) ; 8.2 (8.2) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo| ; 17.9 (17.9) ; 18.8 (18.8) ; 0.9 (0.9) ; 0.1 (0.1) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo| ; 17.6 (17.6) ; 17.6 (17.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo| ; 7.0 (7.0) ; 7.0 (7.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo| ; 8.0 (8.0) ; 8.2 (8.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo| ; 18.8 (18.8) ; 20.3 (20.3) ; 1.8 (1.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo| ; 20.5 (20.5) ; 20.8 (20.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo| ; 2.9 (2.9) ; 3.1 (3.1) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo| ; 18.2 (18.2) ; 20.1 (20.1) ; 1.9 (1.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo| ; 20.5 (20.5) ; 20.5 (20.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo| ; 2.6 (2.6) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo| ; 2.5 (2.5) ; 3.1 (3.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo| ; 17.3 (17.3) ; 18.3 (18.3) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo| ; 18.1 (18.1) ; 18.7 (18.7) ; 1.0 (1.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo| ; 8.3 (8.3) ; 8.3 (8.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo| ; 9.0 (9.0) ; 9.2 (9.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo| ; 20.0 (20.0) ; 20.5 (20.5) ; 1.3 (1.3) ; 0.8 (0.8) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo| ; 20.3 (20.3) ; 20.6 (20.6) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo| ; 2.8 (2.8) ; 3.2 (3.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo| ; 19.4 (19.4) ; 20.5 (20.5) ; 1.2 (1.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo| ; 20.5 (20.5) ; 20.6 (20.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ;
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; |altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent| ; 62.2 (28.7) ; 62.2 (30.7) ; 0.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 114 (55) ; 26 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ; altera_merlin_axi_master_ni ; ulight_fifo ;
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; |altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent| ; 61.8 (29.2) ; 65.0 (32.7) ; 3.2 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 116 (57) ; 26 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ; altera_merlin_axi_master_ni ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 31.5 (31.5) ; 31.5 (31.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 59 (59) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 32.3 (32.3) ; 32.3 (32.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 59 (59) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:auto_start_s1_burst_adapter| ; 42.4 (0.0) ; 45.2 (0.0) ; 2.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:auto_start_s1_burst_adapter| ; 44.3 (0.0) ; 47.3 (0.0) ; 3.0 (0.0) ; 0.1 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.4 (42.2) ; 45.2 (44.9) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.3 (44.1) ; 47.3 (47.0) ; 3.0 (3.0) ; 0.1 (0.1) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:clock_sel_s1_burst_adapter| ; 44.2 (0.0) ; 46.7 (0.0) ; 2.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 64 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:clock_sel_s1_burst_adapter| ; 44.3 (0.0) ; 47.2 (0.0) ; 2.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (0) ; 64 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.2 (44.0) ; 46.7 (46.4) ; 2.4 (2.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.3 (44.1) ; 47.2 (46.9) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (66) ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter| ; 38.8 (0.0) ; 41.3 (0.0) ; 2.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter| ; 41.2 (0.0) ; 43.6 (0.0) ; 2.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 38.8 (37.8) ; 41.3 (40.8) ; 2.5 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (55) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 41.2 (40.9) ; 43.6 (43.1) ; 2.3 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.5 (0.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter| ; 38.3 (0.0) ; 42.0 (0.0) ; 3.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter| ; 39.8 (0.0) ; 41.5 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 38.3 (37.6) ; 42.0 (41.7) ; 3.7 (4.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (55) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.8 (39.5) ; 41.5 (41.2) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter| ; 35.4 (0.0) ; 38.3 (0.0) ; 2.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter| ; 38.8 (0.0) ; 40.4 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 35.4 (34.8) ; 38.3 (37.3) ; 2.9 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 38.8 (38.5) ; 40.4 (40.1) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.7 (0.7) ; 1.0 (1.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:data_info_s1_burst_adapter| ; 36.0 (0.0) ; 38.8 (0.0) ; 2.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:data_info_s1_burst_adapter| ; 39.0 (0.0) ; 40.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.0 (35.3) ; 38.8 (38.3) ; 2.8 (2.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.0 (38.7) ; 40.5 (40.5) ; 1.5 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.6 (0.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter| ; 42.5 (0.0) ; 45.1 (0.0) ; 2.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter| ; 44.6 (0.0) ; 48.7 (0.0) ; 4.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.5 (42.2) ; 45.1 (44.6) ; 2.6 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (63) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.6 (44.3) ; 48.7 (48.4) ; 4.1 (4.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.5 (0.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter| ; 36.8 (0.0) ; 38.4 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter| ; 39.6 (0.0) ; 41.5 (0.0) ; 1.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.8 (36.1) ; 38.4 (38.1) ; 1.7 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.6 (39.3) ; 41.5 (41.2) ; 1.9 (1.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter| ; 36.3 (0.0) ; 38.2 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter| ; 39.8 (0.0) ; 43.5 (0.0) ; 3.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.3 (35.9) ; 38.2 (37.9) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (51) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.8 (39.5) ; 43.5 (43.2) ; 3.7 (3.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter| ; 36.7 (0.0) ; 39.8 (0.0) ; 3.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter| ; 39.3 (0.0) ; 41.6 (0.0) ; 2.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.7 (36.4) ; 39.8 (39.8) ; 3.0 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (51) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.3 (39.0) ; 41.6 (41.2) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter| ; 39.0 (0.0) ; 42.6 (0.0) ; 3.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter| ; 39.8 (0.0) ; 41.5 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.0 (38.3) ; 42.6 (41.9) ; 3.6 (3.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (55) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.8 (39.3) ; 41.5 (41.5) ; 1.7 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.7 (0.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:fsm_info_s1_burst_adapter| ; 37.9 (0.0) ; 41.7 (0.0) ; 3.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 55 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:fsm_info_s1_burst_adapter| ; 40.2 (0.0) ; 44.7 (0.0) ; 4.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 61 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 37.9 (37.6) ; 41.7 (41.2) ; 3.8 (3.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 55 (54) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 40.2 (39.8) ; 44.7 (44.3) ; 4.5 (4.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 61 (60) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.5 (0.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter| ; 47.4 (0.0) ; 51.8 (0.0) ; 4.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (0) ; 66 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter| ; 44.7 (0.0) ; 48.1 (0.0) ; 3.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 66 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 47.4 (47.2) ; 51.8 (51.6) ; 4.4 (4.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (66) ; 66 (66) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.7 (44.4) ; 48.1 (47.8) ; 3.4 (3.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 66 (66) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:link_disable_s1_burst_adapter| ; 42.4 (0.0) ; 45.3 (0.0) ; 2.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:link_disable_s1_burst_adapter| ; 45.7 (0.0) ; 49.6 (0.0) ; 3.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.4 (42.2) ; 45.3 (45.1) ; 2.9 (2.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 45.7 (45.4) ; 49.6 (49.3) ; 3.9 (3.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:link_start_s1_burst_adapter| ; 42.3 (0.0) ; 45.6 (0.0) ; 3.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:link_start_s1_burst_adapter| ; 43.4 (0.0) ; 45.8 (0.0) ; 2.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.3 (42.1) ; 45.6 (45.3) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (63) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 43.4 (43.2) ; 45.8 (45.6) ; 2.4 (2.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter| ; 36.7 (0.0) ; 41.1 (0.0) ; 4.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter| ; 39.3 (0.0) ; 40.8 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.7 (36.0) ; 41.1 (40.2) ; 4.4 (4.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.3 (38.9) ; 40.8 (40.6) ; 1.6 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.7 (0.7) ; 0.8 (0.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter| ; 36.8 (0.0) ; 39.4 (0.0) ; 2.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter| ; 41.5 (0.0) ; 42.3 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.8 (36.4) ; 39.4 (39.4) ; 2.7 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (51) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 41.5 (41.2) ; 42.3 (42.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter| ; 45.6 (0.0) ; 49.7 (0.0) ; 4.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 69 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter| ; 47.2 (0.0) ; 52.6 (0.0) ; 5.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 69 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 45.6 (45.3) ; 49.7 (49.4) ; 4.1 (4.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 69 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 47.2 (47.0) ; 52.6 (52.3) ; 5.3 (5.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 69 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter| ; 43.0 (0.0) ; 45.4 (0.0) ; 2.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter| ; 46.0 (0.0) ; 47.6 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 70 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 43.0 (42.7) ; 45.4 (45.4) ; 2.4 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 46.0 (45.8) ; 47.6 (47.3) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 70 (69) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter| ; 36.3 (0.0) ; 39.9 (0.0) ; 3.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter| ; 40.5 (0.0) ; 42.3 (0.0) ; 1.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.3 (35.4) ; 39.9 (39.3) ; 3.7 (3.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 40.5 (40.2) ; 42.3 (42.3) ; 1.8 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.6 (0.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter| ; 44.8 (0.0) ; 47.1 (0.0) ; 2.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 70 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter| ; 46.8 (0.0) ; 50.0 (0.0) ; 3.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 70 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.8 (44.6) ; 47.1 (46.8) ; 2.2 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 70 (70) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 46.8 (46.6) ; 50.0 (49.7) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 70 (70) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter| ; 42.2 (0.0) ; 46.2 (0.0) ; 4.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter| ; 45.7 (0.0) ; 48.0 (0.0) ; 2.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.2 (41.9) ; 46.2 (45.9) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (63) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 45.7 (45.5) ; 48.0 (47.7) ; 2.2 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ;
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; |altera_merlin_slave_agent:auto_start_s1_agent| ; 16.2 (5.8) ; 16.7 (6.1) ; 0.5 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:auto_start_s1_agent| ; 14.8 (5.3) ; 14.8 (5.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 10.4 (10.4) ; 10.6 (10.6) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:clock_sel_s1_agent| ; 15.7 (5.8) ; 16.3 (6.3) ; 0.7 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 27 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:clock_sel_s1_agent| ; 15.3 (5.7) ; 15.5 (5.7) ; 0.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 27 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 10.0 (10.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.8 (9.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:counter_rx_fifo_s1_agent| ; 12.3 (2.2) ; 12.3 (2.7) ; 0.0 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:counter_rx_fifo_s1_agent| ; 12.2 (2.7) ; 12.2 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.7 (9.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:counter_tx_fifo_s1_agent| ; 12.1 (2.2) ; 12.1 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:counter_tx_fifo_s1_agent| ; 12.0 (2.5) ; 13.2 (2.8) ; 1.1 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.6 (9.6) ; 10.3 (10.3) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:data_flag_rx_s1_agent| ; 12.3 (2.3) ; 12.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:data_flag_rx_s1_agent| ; 12.2 (2.2) ; 12.2 (2.2) ; 0.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 10.0 (10.0) ; 10.0 (10.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 10.0 (10.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:data_info_s1_agent| ; 12.5 (2.6) ; 12.5 (2.8) ; 0.0 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:data_info_s1_agent| ; 11.7 (2.2) ; 12.6 (2.4) ; 0.9 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.7 (9.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 10.2 (10.2) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:data_read_en_rx_s1_agent| ; 15.1 (5.7) ; 15.1 (5.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:data_read_en_rx_s1_agent| ; 15.3 (5.5) ; 17.5 (6.3) ; 2.2 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.4 (9.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 11.2 (11.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent| ; 11.8 (2.3) ; 11.8 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent| ; 11.8 (2.3) ; 11.8 (2.3) ; 0.0 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent| ; 12.4 (2.2) ; 12.8 (3.3) ; 0.4 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent| ; 12.7 (2.5) ; 13.8 (2.7) ; 1.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.4 (9.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 11.2 (11.2) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:fifo_full_rx_status_s1_agent| ; 11.7 (2.5) ; 11.7 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:fifo_full_rx_status_s1_agent| ; 12.1 (2.2) ; 12.1 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.2 (9.2) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:fifo_full_tx_status_s1_agent| ; 11.9 (2.4) ; 11.9 (2.5) ; 0.0 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:fifo_full_tx_status_s1_agent| ; 12.1 (2.1) ; 12.1 (2.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.4 (9.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 10.0 (10.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:fsm_info_s1_agent| ; 12.2 (2.9) ; 12.2 (2.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:fsm_info_s1_agent| ; 11.8 (2.2) ; 12.0 (2.3) ; 0.2 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.2 (9.2) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.7 (9.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:led_pio_test_s1_agent| ; 14.9 (5.5) ; 14.9 (5.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:led_pio_test_s1_agent| ; 14.9 (4.8) ; 16.6 (5.8) ; 1.7 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.4 (9.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 10.8 (10.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:link_disable_s1_agent| ; 16.1 (5.6) ; 16.5 (5.6) ; 0.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:link_disable_s1_agent| ; 14.9 (5.4) ; 16.0 (6.8) ; 1.1 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 10.0 (10.0) ; 10.9 (10.9) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.2 (9.2) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:link_start_s1_agent| ; 15.6 (5.3) ; 15.6 (5.7) ; 0.0 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:link_start_s1_agent| ; 15.2 (5.6) ; 15.5 (5.8) ; 0.3 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.9 (9.9) ; 9.9 (9.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.7 (9.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:timecode_ready_rx_s1_agent| ; 12.6 (2.5) ; 12.6 (2.8) ; 0.0 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:timecode_ready_rx_s1_agent| ; 11.6 (2.2) ; 11.7 (2.2) ; 0.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.3 (9.3) ; 9.5 (9.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:timecode_rx_s1_agent| ; 12.8 (2.6) ; 13.2 (3.1) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:timecode_rx_s1_agent| ; 11.9 (2.2) ; 12.4 (2.5) ; 0.5 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 10.2 (10.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.9 (9.9) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:timecode_tx_data_s1_agent| ; 16.5 (6.3) ; 17.6 (6.3) ; 1.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:timecode_tx_data_s1_agent| ; 15.5 (5.3) ; 15.8 (5.6) ; 0.2 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 10.0 (10.0) ; 11.2 (11.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 10.2 (10.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
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; |altera_merlin_slave_agent:timecode_tx_enable_s1_agent| ; 16.0 (5.7) ; 16.2 (5.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_slave_agent:timecode_tx_enable_s1_agent| ; 15.1 (5.4) ; 15.7 (5.8) ; 0.6 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
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; |altera_merlin_burst_uncompressor:uncompressor| ; 10.3 (10.3) ; 10.3 (10.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.8 (9.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:timecode_tx_ready_s1_agent| ; 12.7 (2.2) ; 13.2 (2.7) ; 0.6 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:timecode_tx_ready_s1_agent| ; 12.1 (2.5) ; 12.1 (2.8) ; 0.0 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.5 (10.5) ; 10.6 (10.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.3 (9.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:write_data_fifo_tx_s1_agent| ; 15.8 (5.4) ; 15.8 (6.0) ; 0.0 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:write_data_fifo_tx_s1_agent| ; 15.5 (5.4) ; 15.5 (5.5) ; 0.0 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.0 (10.0) ; 10.0 (10.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_agent:write_en_tx_s1_agent| ; 15.0 (5.9) ; 15.0 (5.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_slave_agent:write_en_tx_s1_agent| ; 14.5 (5.2) ; 14.5 (5.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.1 (9.1) ; 9.1 (9.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.3 (9.3) ; 9.3 (9.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ;
|
; |altera_merlin_slave_translator:auto_start_s1_translator| ; 2.3 (2.3) ; 3.3 (3.3) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:auto_start_s1_translator| ; 2.1 (2.1) ; 3.3 (3.3) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:clock_sel_s1_translator| ; 2.7 (2.7) ; 3.7 (3.7) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:clock_sel_s1_translator| ; 3.1 (3.1) ; 3.8 (3.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:counter_rx_fifo_s1_translator| ; 1.5 (1.5) ; 4.1 (4.1) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:counter_rx_fifo_s1_translator| ; 2.6 (2.6) ; 3.4 (3.4) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:counter_tx_fifo_s1_translator| ; 2.2 (2.2) ; 4.1 (4.1) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:counter_tx_fifo_s1_translator| ; 1.8 (1.8) ; 3.2 (3.2) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:data_flag_rx_s1_translator| ; 1.2 (1.2) ; 4.8 (4.8) ; 3.6 (3.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:data_flag_rx_s1_translator| ; 3.0 (3.0) ; 4.4 (4.4) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:data_info_s1_translator| ; 1.7 (1.7) ; 6.3 (6.3) ; 4.6 (4.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:data_info_s1_translator| ; 1.8 (1.8) ; 3.2 (3.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:data_read_en_rx_s1_translator| ; 2.4 (2.4) ; 3.1 (3.1) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:data_read_en_rx_s1_translator| ; 2.2 (2.2) ; 2.8 (2.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator| ; 2.1 (2.1) ; 2.2 (2.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator| ; 1.3 (1.3) ; 1.8 (1.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator| ; 2.2 (2.2) ; 2.8 (2.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator| ; 1.2 (1.2) ; 2.1 (2.1) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_full_rx_status_s1_translator| ; 2.1 (2.1) ; 3.2 (3.2) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_full_rx_status_s1_translator| ; 1.1 (1.1) ; 1.9 (1.9) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_full_tx_status_s1_translator| ; 1.6 (1.6) ; 3.0 (3.0) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fifo_full_tx_status_s1_translator| ; 1.4 (1.4) ; 2.1 (2.1) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fsm_info_s1_translator| ; 1.8 (1.8) ; 3.7 (3.7) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:fsm_info_s1_translator| ; 1.9 (1.9) ; 2.5 (2.5) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:led_pio_test_s1_translator| ; 3.8 (3.8) ; 3.7 (3.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:led_pio_test_s1_translator| ; 3.6 (3.6) ; 3.8 (3.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:link_disable_s1_translator| ; 2.4 (2.4) ; 3.2 (3.2) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:link_disable_s1_translator| ; 2.5 (2.5) ; 2.8 (2.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:link_start_s1_translator| ; 2.3 (2.3) ; 3.2 (3.2) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:link_start_s1_translator| ; 2.3 (2.3) ; 3.0 (3.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
|
; |altera_merlin_slave_translator:timecode_ready_rx_s1_translator| ; 2.2 (2.2) ; 2.8 (2.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
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; |altera_merlin_slave_translator:timecode_ready_rx_s1_translator| ; 1.7 (1.7) ; 2.0 (2.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
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; |altera_merlin_slave_translator:timecode_rx_s1_translator| ; 2.8 (2.8) ; 4.2 (4.2) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
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; |altera_merlin_slave_translator:timecode_rx_s1_translator| ; 2.4 (2.4) ; 5.0 (5.0) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
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; |altera_merlin_slave_translator:timecode_tx_data_s1_translator| ; 4.2 (4.2) ; 5.0 (5.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
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; |altera_merlin_slave_translator:timecode_tx_data_s1_translator| ; 3.5 (3.5) ; 4.5 (4.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
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; |altera_merlin_slave_translator:timecode_tx_enable_s1_translator| ; 2.8 (2.8) ; 3.2 (3.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
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; |altera_merlin_slave_translator:timecode_tx_enable_s1_translator| ; 2.2 (2.2) ; 2.9 (2.9) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
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; |altera_merlin_slave_translator:timecode_tx_ready_s1_translator| ; 2.1 (2.1) ; 3.0 (3.0) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
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; |altera_merlin_slave_translator:timecode_tx_ready_s1_translator| ; 1.0 (1.0) ; 1.6 (1.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
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; |altera_merlin_slave_translator:write_data_fifo_tx_s1_translator| ; 4.8 (4.8) ; 5.0 (5.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
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; |altera_merlin_slave_translator:write_data_fifo_tx_s1_translator| ; 4.2 (4.2) ; 5.1 (5.1) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
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; |altera_merlin_slave_translator:write_en_tx_s1_translator| ; 2.4 (2.4) ; 3.1 (3.1) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
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; |altera_merlin_slave_translator:write_en_tx_s1_translator| ; 2.3 (2.3) ; 2.8 (2.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ;
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; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter| ; 14.5 (14.5) ; 14.5 (14.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (11) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ;
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; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter| ; 15.3 (15.3) ; 15.3 (15.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ;
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; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter| ; 12.8 (12.8) ; 13.5 (13.5) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ;
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; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter| ; 14.4 (14.4) ; 14.4 (14.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux| ; 15.7 (15.7) ; 17.7 (17.7) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 31 (31) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux| ; 18.4 (18.4) ; 20.1 (20.1) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 35 (35) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001| ; 23.8 (23.8) ; 25.3 (25.3) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 40 (40) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001| ; 31.6 (31.6) ; 31.6 (31.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux| ; 13.1 (10.8) ; 13.3 (11.2) ; 0.2 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 37 (33) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux| ; 11.7 (9.8) ; 12.5 (10.5) ; 0.8 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 37 (32) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 2.1 (2.1) ; 2.1 (2.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 2.0 (2.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001| ; 6.4 (6.4) ; 6.4 (6.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001| ; 7.0 (7.0) ; 8.1 (8.1) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002| ; 6.3 (6.3) ; 7.1 (7.1) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002| ; 7.0 (7.0) ; 8.2 (8.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003| ; 6.7 (6.7) ; 7.7 (7.7) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003| ; 6.7 (6.7) ; 7.8 (7.8) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004| ; 12.8 (10.2) ; 13.7 (11.1) ; 1.0 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004| ; 11.1 (9.6) ; 12.2 (10.7) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 2.6 (2.6) ; 2.7 (2.7) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005| ; 6.1 (6.1) ; 6.2 (6.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005| ; 6.8 (6.8) ; 7.2 (7.2) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006| ; 6.4 (6.4) ; 6.4 (6.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006| ; 7.1 (7.1) ; 8.0 (8.0) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007| ; 11.9 (10.6) ; 12.6 (10.8) ; 0.7 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007| ; 12.3 (10.3) ; 12.7 (10.8) ; 0.3 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 1.3 (1.3) ; 1.8 (1.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008| ; 13.7 (9.7) ; 14.7 (10.4) ; 1.1 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008| ; 12.0 (9.8) ; 11.9 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 4.0 (4.0) ; 4.3 (4.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 1.9 (1.9) ; 2.2 (2.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009| ; 12.8 (9.5) ; 14.4 (11.1) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009| ; 11.5 (9.7) ; 12.4 (10.6) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010| ; 14.5 (11.6) ; 16.7 (12.7) ; 2.2 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 42 (37) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010| ; 14.5 (12.5) ; 14.5 (12.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 42 (37) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 2.9 (2.9) ; 4.0 (4.0) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011| ; 11.3 (9.3) ; 12.5 (10.7) ; 1.2 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011| ; 11.6 (9.6) ; 12.8 (10.5) ; 1.3 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 2.0 (2.0) ; 2.3 (2.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012| ; 6.3 (6.3) ; 6.8 (6.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012| ; 6.6 (6.6) ; 6.6 (6.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013| ; 6.4 (6.4) ; 6.9 (6.9) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013| ; 6.4 (6.4) ; 6.4 (6.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014| ; 13.8 (11.2) ; 14.8 (12.2) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 41 (36) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014| ; 12.6 (10.8) ; 14.0 (12.2) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 40 (35) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 2.7 (2.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015| ; 11.7 (9.3) ; 12.3 (10.1) ; 0.7 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 32 (28) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015| ; 10.6 (8.6) ; 12.1 (10.1) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (28) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 2.2 (2.2) ; 2.2 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016| ; 6.8 (6.8) ; 7.4 (7.4) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (23) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016| ; 6.8 (6.8) ; 6.8 (6.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017| ; 6.7 (6.7) ; 6.7 (6.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017| ; 6.3 (6.3) ; 6.3 (6.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018| ; 13.0 (9.7) ; 13.0 (9.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 36 (31) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018| ; 11.4 (9.9) ; 13.2 (10.7) ; 1.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 35 (31) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |altera_merlin_arbitrator:arb| ; 1.5 (1.5) ; 2.5 (2.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019| ; 6.0 (6.0) ; 6.7 (6.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019| ; 6.5 (6.5) ; 6.5 (6.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020| ; 6.7 (6.7) ; 6.7 (6.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020| ; 6.7 (6.7) ; 7.1 (7.1) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021| ; 6.3 (6.3) ; 6.3 (6.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021| ; 6.4 (6.4) ; 6.7 (6.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ;
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; |ulight_fifo_mm_interconnect_0_router:router| ; 14.3 (14.3) ; 17.3 (17.3) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_router:router| ; 10.2 (10.2) ; 13.2 (13.2) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (28) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_router:router_001| ; 21.0 (21.0) ; 23.5 (23.5) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 44 (44) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001 ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_router:router_001| ; 16.0 (16.0) ; 18.3 (18.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 40 (40) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001 ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux| ; 1.1 (1.1) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux| ; 1.2 (1.2) ; 1.3 (1.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004| ; 1.1 (1.1) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004| ; 1.2 (1.2) ; 1.3 (1.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007| ; 0.9 (0.9) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007| ; 1.2 (1.2) ; 1.3 (1.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008| ; 1.1 (1.1) ; 1.3 (1.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008| ; 1.1 (1.1) ; 1.2 (1.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009| ; 1.6 (1.6) ; 1.6 (1.6) ; 0.1 (0.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009| ; 1.5 (1.5) ; 1.7 (1.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010| ; 1.5 (1.5) ; 1.6 (1.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010| ; 1.3 (1.3) ; 1.8 (1.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.1 (0.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014| ; 1.4 (1.4) ; 1.8 (1.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015| ; 1.4 (1.4) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015| ; 1.5 (1.5) ; 1.7 (1.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018| ; 0.8 (0.8) ; 1.2 (1.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018| ; 0.8 (0.8) ; 0.9 (0.9) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux| ; 36.5 (36.5) ; 40.3 (40.3) ; 5.2 (5.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 88 (88) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux| ; 37.3 (37.3) ; 36.9 (36.9) ; 0.3 (0.3) ; 0.7 (0.7) ; 0.0 (0.0) ; 88 (88) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001| ; 128.4 (128.4) ; 156.2 (156.2) ; 29.3 (29.3) ; 1.5 (1.5) ; 0.0 (0.0) ; 300 (300) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001 ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ;
|
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001| ; 127.2 (127.2) ; 135.9 (135.9) ; 10.3 (10.3) ; 1.5 (1.5) ; 0.0 (0.0) ; 294 (294) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001 ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ;
|
; |ulight_fifo_pll_0:pll_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0 ; ulight_fifo_pll_0 ; ulight_fifo ;
|
; |ulight_fifo_pll_0:pll_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0 ; ulight_fifo_pll_0 ; ulight_fifo ;
|
; |altera_pll:altera_pll_i| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i ; altera_pll ; work ;
|
; |altera_pll:altera_pll_i| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i ; altera_pll ; work ;
|
; |altera_cyclonev_pll:cyclonev_pll| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll ; altera_cyclonev_pll ; work ;
|
; |altera_cyclonev_pll:cyclonev_pll| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll ; altera_cyclonev_pll ; work ;
|
; |altera_cyclonev_pll_base:fpll_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0 ; altera_cyclonev_pll_base ; work ;
|
; |altera_cyclonev_pll_base:fpll_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0 ; altera_cyclonev_pll_base ; work ;
|
; |ulight_fifo_timecode_rx:timecode_rx| ; 4.2 (4.2) ; 4.2 (4.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx ; ulight_fifo_timecode_rx ; ulight_fifo ;
|
; |ulight_fifo_timecode_rx:timecode_rx| ; 2.8 (2.8) ; 3.3 (3.3) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx ; ulight_fifo_timecode_rx ; ulight_fifo ;
|
; |ulight_fifo_timecode_tx_data:timecode_tx_data| ; 2.3 (2.3) ; 6.3 (6.3) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data ; ulight_fifo_timecode_tx_data ; ulight_fifo ;
|
; |ulight_fifo_timecode_tx_data:timecode_tx_data| ; 3.3 (3.3) ; 6.0 (6.0) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data ; ulight_fifo_timecode_tx_data ; ulight_fifo ;
|
; |ulight_fifo_write_data_fifo_tx:write_data_fifo_tx| ; 2.6 (2.6) ; 7.1 (7.1) ; 4.5 (4.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx ; ulight_fifo_write_data_fifo_tx ; ulight_fifo ;
|
; |ulight_fifo_write_data_fifo_tx:write_data_fifo_tx| ; 2.5 (2.5) ; 7.6 (7.6) ; 5.1 (5.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx ; ulight_fifo_write_data_fifo_tx ; ulight_fifo ;
|
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------+
|
; Delay Chain Summary ;
|
; Delay Chain Summary ;
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
|
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
; dout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
; sout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
; LED[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; dout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
; LED[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; sout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
; LED[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;
|
; LED[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;
|
; LED[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;
|
; LED[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;
|
; LED[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ;
|
; KEY[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; KEY[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; LED[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; LED[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
|
; FPGA_CLK1_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; FPGA_CLK1_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; KEY[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; KEY[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; din_a ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; din_a ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; sin_a ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; sin_a ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; dout_a(n) ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
; dout_a(n) ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ;
|
| Line 1537... |
Line 1737... |
; din_a(n) ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; din_a(n) ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; sin_a(n) ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
; sin_a(n) ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------+
|
+---------------------------------------------------------------------------------------------------------------------------------------------+
|
; Pad To Core Delay Chain Fanout ;
|
; Pad To Core Delay Chain Fanout ;
|
+----------------------------------------------------------------------------------------------+-------------------+---------+
|
+---------------------------------------------------------------------------------------------------------------+-------------------+---------+
|
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
|
; Source Pin / Fanout ; Pad To Core Index ; Setting ;
|
+----------------------------------------------------------------------------------------------+-------------------+---------+
|
+---------------------------------------------------------------------------------------------------------------+-------------------+---------+
|
; KEY[0] ; ; ;
|
; KEY[0] ; ; ;
|
; FPGA_CLK1_50 ; ; ;
|
; FPGA_CLK1_50 ; ; ;
|
; KEY[1] ; ; ;
|
; KEY[1] ; ; ;
|
; - debounce_db:db_system_spwulight_b|PB_down~0 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|PB_down~0 ; 0 ; 0 ;
|
|
; - debounce_db:db_system_spwulight_b|aux_pb~0 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~0 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~0 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter[13]~1 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~1 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~2 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~2 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~3 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~3 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~4 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~4 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~5 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~5 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~6 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~6 ; 0 ; 0 ;
|
| Line 1562... |
Line 1763... |
; - debounce_db:db_system_spwulight_b|counter~11 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~11 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~12 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~12 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~13 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~13 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~14 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~14 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~15 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~15 ; 0 ; 0 ;
|
; - debounce_db:db_system_spwulight_b|counter~16 ; 0 ; 0 ;
|
|
; - debounce_db:db_system_spwulight_b|PB_down~1 ; 0 ; 0 ;
|
|
; - debounce_db:db_system_spwulight_b|aux_pb~0 ; 0 ; 0 ;
|
|
; din_a ; ; ;
|
; din_a ; ; ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_1 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_0 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|control_bit_found ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_1 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_1 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_0 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_0 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~3 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_1 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_0 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|control_bit_found ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 0 ; 0 ;
|
; sin_a ; ; ;
|
; sin_a ; ; ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~4 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 1 ; 0 ;
|
; din_a(n) ; ; ;
|
; din_a(n) ; ; ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_1 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_0 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|control_bit_found ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_1 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_1 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_0 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_0 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~3 ; 0 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_1 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_0 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|control_bit_found ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 0 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 0 ; 0 ;
|
; sin_a(n) ; ; ;
|
; sin_a(n) ; ; ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~4 ; 1 ; 0 ;
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 1 ; 0 ;
|
+----------------------------------------------------------------------------------------------+-------------------+---------+
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 1 ; 0 ;
|
|
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 1 ; 0 ;
|
|
+---------------------------------------------------------------------------------------------------------------+-------------------+---------+
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Control Signals ;
|
; Control Signals ;
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
|
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
; FPGA_CLK1_50 ; PIN_Y13 ; 3124 ; Clock ; yes ; Global Clock ; GCLK5 ; -- ;
|
; FPGA_CLK1_50 ; PIN_Y13 ; 3073 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ;
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FF_X27_Y11_N29 ; 1270 ; Clock ; no ; -- ; -- ; -- ;
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FF_X48_Y7_N35 ; 1319 ; Clock ; no ; -- ; -- ; -- ;
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FF_X13_Y17_N26 ; 60 ; Clock ; no ; -- ; -- ; -- ;
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FF_X61_Y4_N41 ; 105 ; Clock ; no ; -- ; -- ; -- ;
|
; debounce_db:db_system_spwulight_b|PB_down~0 ; MLABCELL_X47_Y1_N18 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; debounce_db:db_system_spwulight_b|aux_pb ; FF_X56_Y3_N59 ; 72 ; Async. clear ; no ; -- ; -- ; -- ;
|
; debounce_db:db_system_spwulight_b|aux_pb ; FF_X47_Y1_N14 ; 127 ; Async. clear ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|always5~1 ; LABCELL_X53_Y3_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; debounce_db:db_system_spwulight_b|counter[13]~1 ; MLABCELL_X47_Y1_N21 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|comb ; LABCELL_X53_Y3_N27 ; 21 ; Clock ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|WideOr7~0 ; LABCELL_X18_Y14_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|counter_neg:cnt_neg|WideOr8~0 ; LABCELL_X51_Y3_N30 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|always1~0 ; LABCELL_X23_Y14_N12 ; 6 ; Clock ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|negedge_clk ; LABCELL_X53_Y3_N39 ; 18 ; Clock ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|always2~0 ; LABCELL_X23_Y14_N48 ; 6 ; Clock ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|state_data_process.01 ; FF_X53_Y3_N11 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|always3~0 ; MLABCELL_X19_Y14_N21 ; 84 ; Clock ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always5~0 ; LABCELL_X48_Y10_N3 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|data[8]~2 ; MLABCELL_X19_Y15_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~0 ; LABCELL_X51_Y9_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|data_l_r[7]~0 ; MLABCELL_X19_Y15_N9 ; 19 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~1 ; LABCELL_X58_Y9_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|data_l_r[7]~1 ; MLABCELL_X19_Y15_N21 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~10 ; LABCELL_X53_Y11_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|is_control ; FF_X23_Y14_N56 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~11 ; LABCELL_X53_Y11_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|ready_control_p_r ; FF_X19_Y15_N20 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~12 ; LABCELL_X58_Y9_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|ready_data_p ; LABCELL_X23_Y14_N39 ; 19 ; Clock ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~13 ; LABCELL_X53_Y11_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|rx_got_time_code~1 ; LABCELL_X18_Y15_N24 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~14 ; LABCELL_X53_Y11_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; detector_tokens:m_x|timecode[7]~0 ; LABCELL_X22_Y15_N9 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~15 ; LABCELL_X53_Y11_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~10 ; LABCELL_X35_Y8_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~16 ; LABCELL_X58_Y9_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~12 ; LABCELL_X27_Y11_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~17 ; LABCELL_X56_Y9_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~14 ; LABCELL_X33_Y8_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~18 ; MLABCELL_X50_Y8_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~15 ; LABCELL_X28_Y7_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~19 ; LABCELL_X54_Y9_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~16 ; LABCELL_X31_Y8_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~2 ; LABCELL_X51_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~18 ; LABCELL_X35_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~20 ; LABCELL_X58_Y8_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~19 ; LABCELL_X35_Y9_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~21 ; MLABCELL_X50_Y8_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~2 ; LABCELL_X33_Y10_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~22 ; MLABCELL_X50_Y8_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~20 ; LABCELL_X35_Y8_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~23 ; LABCELL_X54_Y9_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~21 ; LABCELL_X33_Y8_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~24 ; LABCELL_X53_Y10_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~22 ; LABCELL_X33_Y10_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~25 ; LABCELL_X51_Y11_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~23 ; LABCELL_X33_Y10_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~26 ; MLABCELL_X50_Y8_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~25 ; LABCELL_X28_Y13_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~27 ; MLABCELL_X50_Y10_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~27 ; MLABCELL_X32_Y12_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~28 ; LABCELL_X51_Y9_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~28 ; LABCELL_X33_Y11_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~29 ; LABCELL_X51_Y9_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~29 ; LABCELL_X28_Y13_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~3 ; LABCELL_X58_Y9_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~3 ; LABCELL_X31_Y8_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~30 ; LABCELL_X51_Y9_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~30 ; MLABCELL_X32_Y12_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~31 ; LABCELL_X51_Y9_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~31 ; MLABCELL_X32_Y12_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~32 ; LABCELL_X51_Y11_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~32 ; MLABCELL_X32_Y12_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~33 ; LABCELL_X58_Y9_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~33 ; MLABCELL_X32_Y12_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~34 ; MLABCELL_X50_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~34 ; LABCELL_X33_Y11_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~35 ; LABCELL_X51_Y11_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~35 ; MLABCELL_X32_Y12_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~36 ; LABCELL_X58_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~37 ; LABCELL_X33_Y11_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~37 ; LABCELL_X58_Y9_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~38 ; LABCELL_X33_Y11_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~38 ; MLABCELL_X50_Y8_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~39 ; LABCELL_X33_Y11_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~39 ; LABCELL_X56_Y9_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~40 ; MLABCELL_X32_Y12_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~4 ; LABCELL_X56_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~41 ; LABCELL_X33_Y11_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~40 ; LABCELL_X58_Y9_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~42 ; LABCELL_X33_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~41 ; LABCELL_X58_Y8_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~44 ; MLABCELL_X32_Y10_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~42 ; LABCELL_X56_Y9_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~45 ; LABCELL_X27_Y11_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~43 ; LABCELL_X58_Y9_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~46 ; LABCELL_X28_Y13_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~44 ; LABCELL_X58_Y8_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~47 ; LABCELL_X28_Y13_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~45 ; LABCELL_X58_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~48 ; LABCELL_X27_Y11_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~46 ; MLABCELL_X50_Y8_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~49 ; LABCELL_X27_Y11_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~47 ; LABCELL_X56_Y9_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~5 ; MLABCELL_X32_Y12_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~48 ; LABCELL_X53_Y10_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~50 ; LABCELL_X27_Y11_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~49 ; LABCELL_X53_Y10_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~51 ; LABCELL_X27_Y11_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~5 ; LABCELL_X58_Y9_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~53 ; LABCELL_X27_Y7_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~50 ; LABCELL_X58_Y8_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~54 ; MLABCELL_X32_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~51 ; LABCELL_X53_Y10_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~55 ; MLABCELL_X32_Y10_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~52 ; LABCELL_X54_Y9_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~56 ; LABCELL_X27_Y7_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~53 ; LABCELL_X53_Y11_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~57 ; MLABCELL_X32_Y10_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~54 ; LABCELL_X56_Y9_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~58 ; MLABCELL_X32_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~55 ; LABCELL_X56_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~59 ; MLABCELL_X32_Y10_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~56 ; LABCELL_X51_Y11_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~6 ; LABCELL_X33_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~57 ; LABCELL_X53_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~60 ; MLABCELL_X32_Y10_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~58 ; MLABCELL_X50_Y10_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~62 ; LABCELL_X33_Y10_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~59 ; MLABCELL_X50_Y10_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~63 ; LABCELL_X27_Y11_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~6 ; MLABCELL_X50_Y8_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~64 ; LABCELL_X28_Y7_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~60 ; LABCELL_X54_Y9_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~66 ; LABCELL_X33_Y8_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~61 ; LABCELL_X54_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~67 ; LABCELL_X31_Y8_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~62 ; LABCELL_X58_Y8_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~68 ; LABCELL_X33_Y8_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~63 ; LABCELL_X53_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~69 ; LABCELL_X31_Y8_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~7 ; LABCELL_X58_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~70 ; LABCELL_X33_Y8_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~8 ; LABCELL_X58_Y9_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~71 ; MLABCELL_X32_Y10_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~9 ; LABCELL_X51_Y11_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~72 ; LABCELL_X27_Y11_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~0 ; MLABCELL_X42_Y5_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~74 ; LABCELL_X35_Y9_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~1 ; MLABCELL_X42_Y6_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~76 ; LABCELL_X35_Y8_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~10 ; MLABCELL_X42_Y8_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~77 ; LABCELL_X33_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~11 ; LABCELL_X40_Y8_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~78 ; LABCELL_X33_Y8_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~12 ; MLABCELL_X42_Y6_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~79 ; LABCELL_X35_Y9_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~13 ; MLABCELL_X42_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~8 ; MLABCELL_X32_Y10_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~14 ; MLABCELL_X42_Y9_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~80 ; LABCELL_X33_Y8_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~15 ; MLABCELL_X42_Y9_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always0~0 ; LABCELL_X31_Y13_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~16 ; LABCELL_X41_Y5_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always1~0 ; LABCELL_X27_Y16_N54 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~17 ; LABCELL_X41_Y6_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always1~2 ; LABCELL_X31_Y13_N15 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~18 ; MLABCELL_X42_Y5_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|block_write ; FF_X28_Y11_N26 ; 67 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~19 ; LABCELL_X41_Y6_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[5]~0 ; LABCELL_X27_Y16_N51 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~2 ; MLABCELL_X42_Y5_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[5]~1 ; LABCELL_X31_Y13_N54 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~20 ; MLABCELL_X42_Y5_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~11 ; LABCELL_X15_Y12_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~21 ; LABCELL_X40_Y5_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~13 ; LABCELL_X18_Y10_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~22 ; LABCELL_X41_Y5_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~14 ; LABCELL_X15_Y12_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~23 ; LABCELL_X40_Y5_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~16 ; MLABCELL_X19_Y10_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~24 ; LABCELL_X40_Y5_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~17 ; MLABCELL_X19_Y10_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~25 ; MLABCELL_X42_Y8_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~19 ; LABCELL_X22_Y10_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~26 ; LABCELL_X40_Y8_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~2 ; LABCELL_X15_Y12_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~27 ; MLABCELL_X42_Y8_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~20 ; LABCELL_X22_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~28 ; LABCELL_X41_Y7_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~22 ; LABCELL_X21_Y14_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~29 ; LABCELL_X41_Y7_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~23 ; LABCELL_X21_Y14_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~3 ; LABCELL_X40_Y8_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~25 ; LABCELL_X22_Y11_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~30 ; MLABCELL_X42_Y5_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~26 ; MLABCELL_X19_Y13_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~31 ; LABCELL_X41_Y7_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~28 ; LABCELL_X15_Y12_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~32 ; MLABCELL_X42_Y6_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~29 ; LABCELL_X17_Y12_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~33 ; LABCELL_X40_Y8_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~30 ; LABCELL_X17_Y10_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~34 ; MLABCELL_X42_Y5_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~31 ; LABCELL_X17_Y12_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~35 ; MLABCELL_X42_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~32 ; LABCELL_X17_Y10_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~36 ; MLABCELL_X42_Y6_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~33 ; LABCELL_X17_Y12_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~37 ; MLABCELL_X42_Y9_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~34 ; LABCELL_X17_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~38 ; MLABCELL_X42_Y6_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~36 ; MLABCELL_X19_Y10_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~39 ; LABCELL_X41_Y9_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~38 ; LABCELL_X17_Y10_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~4 ; LABCELL_X41_Y5_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~39 ; LABCELL_X18_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~40 ; LABCELL_X40_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~4 ; LABCELL_X15_Y12_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~41 ; MLABCELL_X42_Y8_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~41 ; LABCELL_X22_Y10_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~42 ; MLABCELL_X42_Y5_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~43 ; LABCELL_X22_Y11_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~43 ; LABCELL_X41_Y7_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~44 ; LABCELL_X17_Y10_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~44 ; MLABCELL_X42_Y6_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~45 ; LABCELL_X17_Y12_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~45 ; MLABCELL_X42_Y9_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~46 ; LABCELL_X17_Y10_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~46 ; MLABCELL_X42_Y5_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~47 ; LABCELL_X22_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~47 ; MLABCELL_X42_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~49 ; LABCELL_X15_Y12_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~48 ; LABCELL_X41_Y6_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~51 ; LABCELL_X15_Y12_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~49 ; LABCELL_X41_Y6_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~52 ; LABCELL_X15_Y12_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~5 ; LABCELL_X41_Y6_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~53 ; LABCELL_X15_Y12_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~50 ; LABCELL_X41_Y6_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~54 ; MLABCELL_X19_Y10_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~51 ; LABCELL_X41_Y6_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~55 ; LABCELL_X15_Y12_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~52 ; MLABCELL_X42_Y6_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~56 ; LABCELL_X18_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~53 ; MLABCELL_X42_Y6_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~57 ; LABCELL_X15_Y12_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~54 ; LABCELL_X41_Y6_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~58 ; MLABCELL_X19_Y13_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~55 ; LABCELL_X40_Y5_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~59 ; MLABCELL_X19_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~56 ; MLABCELL_X42_Y6_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~6 ; LABCELL_X15_Y12_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~57 ; LABCELL_X40_Y8_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~60 ; LABCELL_X22_Y10_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~58 ; LABCELL_X41_Y5_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~61 ; LABCELL_X22_Y10_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~59 ; LABCELL_X40_Y8_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~62 ; MLABCELL_X19_Y13_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~6 ; LABCELL_X40_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~63 ; MLABCELL_X19_Y13_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~60 ; MLABCELL_X42_Y9_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~64 ; MLABCELL_X19_Y13_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~61 ; MLABCELL_X42_Y9_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~65 ; LABCELL_X22_Y11_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~62 ; LABCELL_X40_Y5_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~66 ; LABCELL_X15_Y12_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~63 ; LABCELL_X41_Y7_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~67 ; LABCELL_X17_Y11_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~7 ; LABCELL_X40_Y8_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~68 ; LABCELL_X17_Y11_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~8 ; MLABCELL_X42_Y8_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~69 ; LABCELL_X17_Y12_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~9 ; MLABCELL_X42_Y9_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~7 ; LABCELL_X15_Y12_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|next_state_data_read.11~0 ; LABCELL_X49_Y5_N48 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~70 ; LABCELL_X15_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write.10 ; FF_X41_Y9_N50 ; 15 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~71 ; LABCELL_X15_Y12_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|enable_tx ; FF_X50_Y3_N32 ; 104 ; Async. clear ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~72 ; LABCELL_X17_Y10_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|rx_resetn ; FF_X49_Y3_N44 ; 75 ; Async. clear ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~73 ; LABCELL_X17_Y11_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; LABCELL_X54_Y5_N51 ; 60 ; Clock ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~74 ; LABCELL_X17_Y10_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|WideOr8~0 ; LABCELL_X53_Y6_N15 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~75 ; LABCELL_X18_Y10_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|negedge_clk ; LABCELL_X53_Y6_N0 ; 17 ; Clock ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~76 ; MLABCELL_X19_Y10_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy|always0~1 ; LABCELL_X56_Y6_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~77 ; LABCELL_X22_Y11_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always0~1 ; LABCELL_X54_Y6_N27 ; 11 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~78 ; LABCELL_X17_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always1~0 ; LABCELL_X54_Y6_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~79 ; LABCELL_X17_Y12_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|state_data_process[0] ; FF_X53_Y6_N44 ; 26 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~80 ; MLABCELL_X19_Y10_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; LABCELL_X48_Y5_N12 ; 1260 ; Async. clear ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~81 ; LABCELL_X22_Y11_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X22_Y29_N56 ; 74 ; Async. clear ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~9 ; MLABCELL_X19_Y10_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X61_Y6_N44 ; 2974 ; Async. clear ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|always1~0 ; LABCELL_X21_Y14_N36 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:auto_start|always0~0 ; LABCELL_X17_Y18_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|block_write ; FF_X21_Y14_N53 ; 45 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx|always0~0 ; LABCELL_X17_Y14_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[5]~0 ; LABCELL_X21_Y14_N27 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:link_disable|always0~0 ; LABCELL_X17_Y19_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|enable_tx ; FF_X28_Y16_N44 ; 65 ; Async. clear ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:link_start|always0~0 ; MLABCELL_X14_Y15_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|rx_resetn ; FF_X28_Y14_N17 ; 109 ; Async. clear ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable|always0~0 ; MLABCELL_X14_Y22_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|WideOr7~0 ; LABCELL_X35_Y15_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx|always0~0 ; LABCELL_X21_Y27_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always11~0 ; MLABCELL_X32_Y15_N15 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel|always0~0 ; LABCELL_X21_Y25_N57 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always1~0 ; LABCELL_X31_Y15_N33 ; 6 ; Clock ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK11 ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always2~0 ; LABCELL_X31_Y15_N24 ; 6 ; Clock ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|always0~0 ; LABCELL_X33_Y16_N48 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; LABCELL_X31_Y15_N39 ; 85 ; Clock ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|always0~0 ; LABCELL_X15_Y18_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|data[9]~0 ; MLABCELL_X32_Y15_N48 ; 17 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X14_Y18_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|last_is_data ; FF_X32_Y15_N56 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y25_N9 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|last_is_data~1 ; MLABCELL_X32_Y15_N57 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y25_N36 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|ready_control_p_r ; FF_X31_Y15_N14 ; 18 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X42_Y11_N24 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|ready_data ; LABCELL_X30_Y15_N12 ; 11 ; Clock ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X37_Y12_N33 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|ready_data_p ; LABCELL_X30_Y15_N27 ; 11 ; Clock ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|always0~0 ; LABCELL_X43_Y11_N27 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_flag[8]~2 ; LABCELL_X31_Y15_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X42_Y12_N36 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|timecode[7]~0 ; LABCELL_X31_Y15_N57 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X45_Y11_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|Selector4~2 ; LABCELL_X17_Y15_N45 ; 17 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X42_Y13_N36 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_counter_receive[0]~6 ; MLABCELL_X14_Y14_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X40_Y10_N9 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_counter_receive[5]~1 ; MLABCELL_X14_Y14_N27 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X37_Y10_N36 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_flag[1]~2 ; MLABCELL_X14_Y16_N36 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X15_Y14_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|global_counter_transfer[0]~4 ; LABCELL_X17_Y16_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X15_Y14_N33 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|global_counter_transfer[0]~8 ; LABCELL_X17_Y16_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y12_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|last_timein_control_flag_tx~1 ; LABCELL_X17_Y16_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y12_N39 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|txdata_flagctrl_tx_last[7]~0 ; LABCELL_X17_Y15_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y9_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; LABCELL_X28_Y16_N15 ; 1232 ; Async. clear ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y9_N0 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X21_Y27_N47 ; 74 ; Async. clear ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y10_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X27_Y1_N38 ; 3025 ; Async. clear ; yes ; Global Clock ; GCLK6 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y10_N33 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:auto_start|always0~0 ; LABCELL_X18_Y30_N15 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X18_Y10_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx|always0~0 ; MLABCELL_X25_Y30_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y10_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:link_disable|always0~0 ; LABCELL_X23_Y26_N51 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X43_Y15_N9 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:link_start|always0~0 ; LABCELL_X28_Y33_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|always0~0 ; LABCELL_X40_Y15_N6 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable|always0~0 ; MLABCELL_X14_Y24_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|always0~0 ; LABCELL_X35_Y15_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx|always0~0 ; LABCELL_X21_Y23_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|always0~0 ; LABCELL_X33_Y16_N51 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel|always0~0 ; LABCELL_X13_Y20_N9 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y19_N51 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK10 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X25_Y19_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|always0~0 ; LABCELL_X11_Y28_N24 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|always0~0 ; LABCELL_X11_Y15_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y30_N42 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|always0~0 ; LABCELL_X11_Y15_N21 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X19_Y32_N24 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X31_Y11_N33 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X14_Y19_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X32_Y11_N51 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|always0~0 ; LABCELL_X13_Y19_N33 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X45_Y11_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X25_Y17_N30 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X37_Y9_N27 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|always0~0 ; LABCELL_X28_Y25_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|always0~0 ; LABCELL_X27_Y27_N45 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y19_N21 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|always0~0 ; LABCELL_X27_Y27_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X25_Y21_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y23_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X17_Y20_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y22_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X13_Y33_N18 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X25_Y8_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X22_Y16_N21 ; 14 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|always0~0 ; LABCELL_X28_Y8_N42 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X25_Y38_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X28_Y19_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y32_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X28_Y19_N30 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y32_N21 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y27_N21 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X14_Y36_N33 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y27_N24 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X15_Y37_N9 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X15_Y20_N0 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X21_Y34_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X17_Y18_N48 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X21_Y34_N21 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y24_N27 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X14_Y34_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X21_Y25_N6 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X14_Y34_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X37_Y13_N39 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X10_Y33_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X37_Y13_N36 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X7_Y33_N3 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X41_Y12_N57 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X27_Y17_N9 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X41_Y12_N42 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|always0~0 ; LABCELL_X28_Y17_N48 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X37_Y14_N45 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|always0~0 ; LABCELL_X17_Y18_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X38_Y14_N42 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|always0~0 ; LABCELL_X11_Y28_N42 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X31_Y11_N3 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y25_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X35_Y10_N6 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X19_Y25_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y16_N15 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|always0~0 ; LABCELL_X27_Y34_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y14_N48 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|always0~0 ; LABCELL_X27_Y34_N6 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X15_Y13_N36 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X14_Y31_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X14_Y13_N30 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X14_Y35_N33 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y11_N57 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X22_Y18_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y11_N57 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X7_Y32_N21 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y9_N12 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|always0~0 ; LABCELL_X21_Y19_N48 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X21_Y9_N30 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|always0~0 ; LABCELL_X17_Y19_N42 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y11_N21 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|always0~0 ; LABCELL_X15_Y24_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y11_N6 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X14_Y22_N9 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X38_Y15_N21 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|always0~0 ; LABCELL_X22_Y38_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X38_Y15_N54 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|always0~0 ; LABCELL_X22_Y38_N18 ; 20 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X30_Y16_N18 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X22_Y20_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X32_Y16_N18 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X22_Y20_N33 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y18_N24 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y24_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y19_N0 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X19_Y24_N42 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y16_N54 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y29_N15 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X11_Y16_N18 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X17_Y31_N18 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X31_Y9_N21 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y24_N3 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X30_Y9_N9 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X14_Y20_N57 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X33_Y12_N54 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y24_N54 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X35_Y9_N36 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X30_Y24_N45 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y26_N24 ; 37 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y21_N39 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X27_Y26_N36 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y21_N0 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X18_Y23_N24 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X13_Y33_N27 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X17_Y23_N6 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X13_Y33_N21 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y12_N33 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y36_N39 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X27_Y12_N9 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y36_N9 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y20_N18 ; 38 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y30_N39 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X30_Y20_N30 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X28_Y32_N33 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y28_N54 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X17_Y37_N6 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X21_Y27_N18 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X17_Y37_N15 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X15_Y18_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y34_N0 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y25_N21 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y34_N30 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X37_Y12_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X10_Y34_N39 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X43_Y12_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X10_Y34_N24 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X42_Y13_N3 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X8_Y34_N48 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X40_Y10_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X7_Y34_N48 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X15_Y14_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X28_Y23_N12 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X18_Y12_N6 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X28_Y20_N21 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y9_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y27_N6 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y10_N9 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X15_Y27_N45 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X18_Y10_N24 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y28_N39 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X43_Y15_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y26_N30 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X35_Y16_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y32_N51 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X25_Y19_N54 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X27_Y32_N21 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X11_Y15_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X18_Y35_N54 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X32_Y11_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X15_Y35_N48 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X38_Y9_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X9_Y35_N18 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X27_Y27_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X9_Y35_N30 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X17_Y22_N21 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X25_Y24_N18 ; 37 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X27_Y8_N24 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y19_N36 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X28_Y19_N45 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y24_N0 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X19_Y27_N36 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y22_N15 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|always1~0 ; LABCELL_X21_Y20_N27 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y38_N15 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|internal_valid~0 ; LABCELL_X23_Y16_N36 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y38_N30 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|always1~0 ; MLABCELL_X25_Y24_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y23_N45 ; 38 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|internal_valid~0 ; LABCELL_X22_Y24_N42 ; 22 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X25_Y22_N9 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 ; MLABCELL_X25_Y24_N33 ; 26 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y27_N0 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|update_grant~0 ; LABCELL_X33_Y12_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y23_N48 ; 33 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|update_grant~0 ; LABCELL_X31_Y9_N9 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X19_Y30_N57 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|update_grant~0 ; MLABCELL_X37_Y14_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X13_Y19_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|update_grant~0 ; MLABCELL_X19_Y16_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X28_Y25_N9 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|update_grant~0 ; LABCELL_X22_Y9_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X28_Y21_N15 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|update_grant~0 ; LABCELL_X15_Y13_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X14_Y33_N36 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|update_grant~0 ; LABCELL_X21_Y16_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X25_Y38_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|update_grant~0 ; LABCELL_X15_Y20_N51 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y32_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|update_grant~0 ; MLABCELL_X19_Y18_N54 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X15_Y37_N57 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|update_grant~0 ; LABCELL_X22_Y20_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X21_Y33_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|update_grant~0 ; LABCELL_X23_Y28_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X14_Y34_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|update_grant~0 ; MLABCELL_X19_Y11_N39 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X7_Y33_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|update_grant~0 ; LABCELL_X22_Y11_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X28_Y17_N9 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|update_grant~0 ; LABCELL_X23_Y26_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X10_Y28_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|update_grant~0 ; LABCELL_X18_Y23_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X19_Y25_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|update_grant~0 ; LABCELL_X27_Y12_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X27_Y34_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|update_grant~0 ; LABCELL_X31_Y11_N18 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X10_Y35_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|update_grant~0 ; LABCELL_X21_Y24_N54 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X6_Y32_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|update_grant~0 ; LABCELL_X38_Y13_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X17_Y19_N6 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|update_grant~0 ; LABCELL_X41_Y12_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X14_Y22_N30 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|update_grant~0 ; LABCELL_X38_Y13_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X22_Y38_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|update_grant~0 ; LABCELL_X30_Y16_N54 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X22_Y20_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y3_N1 ; 24 ; Clock ; yes ; Global Clock ; GCLK8 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X19_Y24_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data|always0~0 ; LABCELL_X30_Y25_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|internal_valid~0 ; MLABCELL_X19_Y31_N45 ; 29 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx|always0~0 ; LABCELL_X30_Y19_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0 ; LABCELL_X22_Y31_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|internal_valid~0 ; LABCELL_X30_Y27_N36 ; 18 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 ; LABCELL_X28_Y27_N3 ; 27 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0 ; LABCELL_X28_Y27_N54 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|update_grant~0 ; MLABCELL_X19_Y31_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|update_grant~0 ; MLABCELL_X19_Y35_N21 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|update_grant~0 ; LABCELL_X10_Y31_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X28_Y30_N12 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|update_grant~0 ; LABCELL_X27_Y30_N33 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|update_grant~0 ; LABCELL_X10_Y34_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|update_grant~0 ; MLABCELL_X19_Y35_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb|top_priority_reg~0 ; LABCELL_X27_Y32_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|update_grant~0 ; LABCELL_X27_Y32_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X23_Y29_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|update_grant~0 ; LABCELL_X23_Y29_N42 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X23_Y28_N42 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|update_grant~0 ; LABCELL_X23_Y28_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X23_Y23_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|update_grant~0 ; LABCELL_X23_Y23_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb|top_priority_reg~0 ; LABCELL_X22_Y27_N57 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|update_grant~0 ; LABCELL_X22_Y27_N33 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|update_grant~0 ; LABCELL_X10_Y34_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|update_grant~0 ; MLABCELL_X19_Y33_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb|top_priority_reg~1 ; MLABCELL_X25_Y24_N48 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|update_grant~0 ; MLABCELL_X25_Y24_N15 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb|top_priority_reg~0 ; LABCELL_X22_Y24_N30 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|update_grant~0 ; LABCELL_X22_Y24_N48 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|update_grant~0 ; MLABCELL_X19_Y38_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|update_grant~0 ; LABCELL_X23_Y36_N27 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X23_Y24_N24 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|update_grant~0 ; LABCELL_X23_Y24_N42 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|update_grant~0 ; LABCELL_X27_Y25_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|update_grant~0 ; LABCELL_X23_Y21_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|update_grant~0 ; LABCELL_X27_Y24_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|top_priority_reg~0 ; LABCELL_X21_Y27_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|update_grant~0 ; LABCELL_X21_Y27_N57 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y3_N1 ; 24 ; Clock ; yes ; Global Clock ; GCLK11 ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data|always0~0 ; LABCELL_X18_Y20_N3 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
; ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx|always0~0 ; LABCELL_X22_Y22_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Global & Other Fast Signals ;
|
; Global & Other Fast Signals ;
|
+------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+
|
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+
|
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
|
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
|
+------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+
|
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+
|
; FPGA_CLK1_50 ; PIN_Y13 ; 3124 ; Global Clock ; GCLK5 ; -- ;
|
; FPGA_CLK1_50 ; PIN_Y13 ; 3073 ; Global Clock ; GCLK4 ; -- ;
|
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X27_Y1_N38 ; 3025 ; Global Clock ; GCLK6 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Global Clock ; GCLK11 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Global Clock ; GCLK10 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fboutclk_wire[0] ; FRACTIONALPLL_X68_Y1_N0 ; 1 ; Global Clock ; -- ; -- ;
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y3_N1 ; 24 ; Global Clock ; GCLK11 ; -- ;
|
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y3_N1 ; 24 ; Global Clock ; GCLK8 ; -- ;
|
+------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+
|
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+
|
|
|
|
|
+-------------------------------------------------------------------------+
|
+----------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Non-Global High Fan-Out Signals ;
|
; Non-Global High Fan-Out Signals ;
|
+---------------------------------------------------------------+---------+
|
+------------------------------------------------------------------------------------------------------------------------------------------+---------+
|
; Name ; Fan-Out ;
|
; Name ; Fan-Out ;
|
+---------------------------------------------------------------+---------+
|
+------------------------------------------------------------------------------------------------------------------------------------------+---------+
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1270 ;
|
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 2974 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; 1232 ;
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1319 ;
|
+---------------------------------------------------------------+---------+
|
; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; 1260 ;
|
|
+------------------------------------------------------------------------------------------------------------------------------------------+---------+
|
|
|
|
|
+-----------------------------------------------------------------------+
|
+------------------------------------------------------------------------+
|
; Routing Usage Summary ;
|
; Routing Usage Summary ;
|
+---------------------------------------------+-------------------------+
|
+---------------------------------------------+--------------------------+
|
; Routing Resource Type ; Usage ;
|
; Routing Resource Type ; Usage ;
|
+---------------------------------------------+-------------------------+
|
+---------------------------------------------+--------------------------+
|
; Block interconnects ; 9,946 / 130,276 ( 8 % ) ;
|
; Block interconnects ; 10,851 / 130,276 ( 8 % ) ;
|
; C12 interconnects ; 143 / 6,848 ( 2 % ) ;
|
; C12 interconnects ; 122 / 6,848 ( 2 % ) ;
|
; C2 interconnects ; 2,297 / 51,436 ( 4 % ) ;
|
; C2 interconnects ; 2,619 / 51,436 ( 5 % ) ;
|
; C4 interconnects ; 1,292 / 25,120 ( 5 % ) ;
|
; C4 interconnects ; 1,582 / 25,120 ( 6 % ) ;
|
; DQS bus muxes ; 0 / 19 ( 0 % ) ;
|
; DQS bus muxes ; 0 / 19 ( 0 % ) ;
|
; DQS-18 I/O buses ; 0 / 19 ( 0 % ) ;
|
; DQS-18 I/O buses ; 0 / 19 ( 0 % ) ;
|
; DQS-9 I/O buses ; 0 / 19 ( 0 % ) ;
|
; DQS-9 I/O buses ; 0 / 19 ( 0 % ) ;
|
; Direct links ; 1,482 / 130,276 ( 1 % ) ;
|
; Direct links ; 1,438 / 130,276 ( 1 % ) ;
|
; Global clocks ; 4 / 16 ( 25 % ) ;
|
; Global clocks ; 3 / 16 ( 19 % ) ;
|
; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
|
; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
|
; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
|
; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
|
; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
|
; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
|
; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
|
; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
|
; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 1 / 6 ( 17 % ) ;
|
; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 1 / 6 ( 17 % ) ;
|
| Line 1997... |
Line 2205... |
; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;
|
; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;
|
; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;
|
; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;
|
; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;
|
; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;
|
; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;
|
; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;
|
; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;
|
; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;
|
; HPS_INTERFACE_HPS2FPGA_INPUTs ; 45 / 165 ( 27 % ) ;
|
; HPS_INTERFACE_HPS2FPGA_INPUTs ; 40 / 165 ( 24 % ) ;
|
; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;
|
; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;
|
; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;
|
; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;
|
; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 101 / 282 ( 36 % ) ;
|
; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 101 / 282 ( 36 % ) ;
|
; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;
|
; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;
|
; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;
|
; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;
|
| Line 2036... |
Line 2244... |
; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
|
; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
|
; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
|
; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
|
; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
|
; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
|
; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
|
; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
|
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;
|
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ;
|
; Local interconnects ; 3,498 / 31,760 ( 11 % ) ;
|
; Local interconnects ; 3,340 / 31,760 ( 11 % ) ;
|
; Quadrant clocks ; 0 / 72 ( 0 % ) ;
|
; Quadrant clocks ; 0 / 72 ( 0 % ) ;
|
; R14 interconnects ; 179 / 6,046 ( 3 % ) ;
|
; R14 interconnects ; 250 / 6,046 ( 4 % ) ;
|
; R14/C12 interconnect drivers ; 267 / 8,584 ( 3 % ) ;
|
; R14/C12 interconnect drivers ; 333 / 8,584 ( 4 % ) ;
|
; R3 interconnects ; 3,386 / 56,712 ( 6 % ) ;
|
; R3 interconnects ; 4,393 / 56,712 ( 8 % ) ;
|
; R6 interconnects ; 5,364 / 131,000 ( 4 % ) ;
|
; R6 interconnects ; 6,014 / 131,000 ( 5 % ) ;
|
; Spine clocks ; 9 / 150 ( 6 % ) ;
|
; Spine clocks ; 6 / 150 ( 4 % ) ;
|
; Wire stub REs ; 0 / 6,650 ( 0 % ) ;
|
; Wire stub REs ; 0 / 6,650 ( 0 % ) ;
|
+---------------------------------------------+-------------------------+
|
+---------------------------------------------+--------------------------+
|
|
|
|
|
+------------------------------------------+
|
+------------------------------------------+
|
; I/O Rules Summary ;
|
; I/O Rules Summary ;
|
+----------------------------------+-------+
|
+----------------------------------+-------+
|
; I/O Rules Statistic ; Total ;
|
; I/O Rules Statistic ; Total ;
|
+----------------------------------+-------+
|
+----------------------------------+-------+
|
; Total I/O Rules ; 28 ;
|
; Total I/O Rules ; 28 ;
|
; Number of I/O Rules Passed ; 7 ;
|
; Number of I/O Rules Passed ; 8 ;
|
; Number of I/O Rules Failed ; 0 ;
|
; Number of I/O Rules Failed ; 0 ;
|
; Number of I/O Rules Unchecked ; 0 ;
|
; Number of I/O Rules Unchecked ; 0 ;
|
; Number of I/O Rules Inapplicable ; 21 ;
|
; Number of I/O Rules Inapplicable ; 20 ;
|
+----------------------------------+-------+
|
+----------------------------------+-------+
|
|
|
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; I/O Rules Details ;
|
; I/O Rules Details ;
|
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------------------------+-------------------+
|
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------------------------+-------------------+
|
; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
|
; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
|
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------------------------+-------------------+
|
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------------------------+-------------------+
|
; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
|
; Pass ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; 0 such failures found. ; I/O ; ;
|
; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
|
; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
|
; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
|
; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
|
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
|
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
|
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
|
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
|
; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
|
; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
|
| Line 2102... |
Line 2310... |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; I/O Rules Matrix ;
|
; I/O Rules Matrix ;
|
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
; Pin/Rules ; IO_000002 ; IO_000003 ; IO_000001 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000022 ; IO_000021 ; IO_000046 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000047 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
|
; Pin/Rules ; IO_000002 ; IO_000003 ; IO_000001 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000022 ; IO_000021 ; IO_000046 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000047 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
|
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
|
; Total Pass ; 0 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 19 ; 16 ;
|
; Total Pass ; 5 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 19 ; 16 ;
|
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
; Total Inapplicable ; 19 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 0 ; 0 ; 3 ;
|
; Total Inapplicable ; 14 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 0 ; 0 ; 3 ;
|
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
; dout_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
|
; sout_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
|
; LED[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; dout_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; sout_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
|
; LED[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
|
; LED[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; LED[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; LED[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; FPGA_CLK1_50 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; FPGA_CLK1_50 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; KEY[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; KEY[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
|
; din_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
; din_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ;
|
| Line 2171... |
Line 2379... |
; Low Junction Temperature ; 0 °C ;
|
; Low Junction Temperature ; 0 °C ;
|
; High Junction Temperature ; 85 °C ;
|
; High Junction Temperature ; 85 °C ;
|
+---------------------------+--------+
|
+---------------------------+--------+
|
|
|
|
|
+------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Estimated Delay Added for Hold Timing Summary ;
|
; Estimated Delay Added for Hold Timing Summary ;
|
+-----------------+----------------------+-------------------+
|
+-------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------+
|
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
|
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
|
+-----------------+----------------------+-------------------+
|
+-------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------+
|
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 417.7 ;
|
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 603.1 ;
|
+-----------------+----------------------+-------------------+
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 152.8 ;
|
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 85.5 ;
|
|
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 83.9 ;
|
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FPGA_CLK1_50 ; 65.3 ;
|
|
; din_a ; din_a ; 47.9 ;
|
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 39.2 ;
|
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 31.9 ;
|
|
; I/O ; din_a ; 25.0 ;
|
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 23.3 ;
|
|
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i,clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 23.3 ;
|
|
+-------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------+
|
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
|
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
|
This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
|
This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; Estimated Delay Added for Hold Timing Details ;
|
; Estimated Delay Added for Hold Timing Details ;
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
+---------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
; Source Register ; Destination Register ; Delay Added in ns ;
|
; Source Register ; Destination Register ; Delay Added in ns ;
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
+---------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2495 ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[3] ; 0.427 ;
|
; din_a ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_0 ; 4.535 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.370 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; detector_tokens:m_x|bit_capture_data:capture_d|bit_d_0 ; 4.290 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.362 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[1] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[1] ; 2.916 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|packet_in_progress ; 0.351 ;
|
; sin_a ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|state_data_process[0] ; 2.828 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|packet_in_progress ; 0.345 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[4] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[4] ; 2.799 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; 0.341 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[7] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[7] ; 2.654 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; 0.338 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[3] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[3] ; 2.645 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[4] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[4] ; 0.331 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[0] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[0] ; 2.639 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; 0.325 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[1] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[1] ; 2.638 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.315 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[2] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[2] ; 2.608 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.315 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[5] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[5] ; 2.608 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.315 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[3] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[3] ; 2.546 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.315 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[5] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[5] ; 2.540 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.315 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_sout_e ; detector_tokens:m_x|info[4] ; 2.341 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.312 ;
|
; detector_tokens:m_x|info[5] ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[5] ; 2.334 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.312 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.run ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[4] ; 2.323 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.312 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.ready ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[1] ; 2.323 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.311 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.error_wait ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[0] ; 2.310 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.311 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[4] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[4] ; 2.289 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.311 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[2] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[2] ; 2.289 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.309 ;
|
; detector_tokens:m_x|info[2] ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[2] ; 2.265 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.308 ;
|
; detector_tokens:m_x|info[4] ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[4] ; 2.253 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.300 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[8] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[8] ; 2.240 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.300 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[0] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[0] ; 2.076 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.300 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[0] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[0] ; 2.018 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.300 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.started ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[2] ; 2.009 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.299 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|open_slot_fct ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p.001 ; 2.008 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|wait_latency_counter[1] ; 0.295 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[6] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[6] ; 2.007 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.294 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.connecting ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[3] ; 2.001 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.294 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[1] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[1] ; 1.991 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.294 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[2] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[2] ; 1.983 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.294 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[3] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[3] ; 1.970 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.293 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|f_empty ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[0] ; 1.934 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.293 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|send_null_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.862 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.293 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[4] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[4] ; 1.857 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[5] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[5] ; 1.839 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_fct ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.702 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_null ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.687 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|ready_tx_timecode ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[0] ; 1.682 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|f_full ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[0] ; 1.670 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_fct_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.599 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|get_rx_got_fct_a ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.connecting ; 1.540 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_data_c_0 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.518 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[5] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[6] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_timec ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|data_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|eop_eep_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|saved_grant[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|fct_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|null_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[6] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[6] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[5] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[5] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_time_code_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_data_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_start ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|enable_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_null_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][77] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|f_empty ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[0] ; 1.346 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|f_full ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[0] ; 1.343 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[0] ; 1.343 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[0] ; 1.318 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|data_out[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[0] ; 1.260 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|overflow_credit_error ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|get_rx_credit_error_b ; 1.259 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|write_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|process_data ; 1.258 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|ready_tx_data ; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read~5 ; 1.255 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.249 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.238 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[10] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.230 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; 0.291 ;
|
; detector_tokens:m_x|counter_neg:cnt_neg|counter_neg[5] ; detector_tokens:m_x|counter_neg:cnt_neg|is_control ; 1.228 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.215 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.290 ;
|
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.169 ;
|
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][74] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[4] ; 0.290 ;
|
; detector_tokens:m_x|counter_neg:cnt_neg|counter_neg[3] ; detector_tokens:m_x|counter_neg:cnt_neg|is_control ; 1.153 ;
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
+---------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+-------------------+
|
Note: This table only shows the top 100 path(s) that have the largest delay added for hold.
|
Note: This table only shows the top 100 path(s) that have the largest delay added for hold.
|
|
|
|
|
+-----------------+
|
+-----------------+
|
; Fitter Messages ;
|
; Fitter Messages ;
|
+-----------------+
|
+-----------------+
|
|
Info (16303): High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation time
|
|
Info (16304): Mode behavior is affected by advanced setting Fitter Effort (default for this mode is Standard Fit)
|
|
Info (16304): Mode behavior is affected by advanced setting Physical Synthesis Effort Level (default for this mode is Normal)
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
|
Info (119006): Selected device 5CSEMA4U23C6 for design "spw_fifo_ulight"
|
Info (119006): Selected device 5CSEMA4U23C6 for design "spw_fifo_ulight"
|
Info (21077): Low junction temperature is 0 degrees C
|
Info (21077): Low junction temperature is 0 degrees C
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Info (21077): High junction temperature is 85 degrees C
|
Info (21077): High junction temperature is 85 degrees C
|
| Line 2308... |
Line 2529... |
Info (184026): differential I/O pin "dout_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "dout_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 9
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Info (184026): differential I/O pin "dout_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "dout_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 9
|
Info (184026): differential I/O pin "sout_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "sout_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 10
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Info (184026): differential I/O pin "sout_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "sout_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 10
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Info (184026): differential I/O pin "din_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "din_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 5
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Info (184026): differential I/O pin "din_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "din_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 5
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Info (184026): differential I/O pin "sin_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "sin_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 6
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Info (184026): differential I/O pin "sin_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "sin_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 6
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Info (184020): Starting Fitter periphery placement operations
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Info (184020): Starting Fitter periphery placement operations
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Warning (177007): PLL(s) placed in location FRACTIONALPLL_X68_Y1_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks
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Info (177008): PLL ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll
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Info (11178): Promoted 2 clocks (2 global)
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Info (11178): Promoted 2 clocks (2 global)
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Info (11162): ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 with 3 fanout uses global clock CLKCTRL_G10
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Info (11162): ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 with 3 fanout uses global clock CLKCTRL_G11
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Info (11162): ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]~CLKENA0 with 24 fanout uses global clock CLKCTRL_G11
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Info (11162): ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]~CLKENA0 with 24 fanout uses global clock CLKCTRL_G8
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Info (11191): Automatically promoted 2 clocks (2 global)
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Info (11191): Automatically promoted 1 clock (1 global)
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Info (11162): FPGA_CLK1_50~inputCLKENA0 with 3124 fanout uses global clock CLKCTRL_G5
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Info (11162): FPGA_CLK1_50~inputCLKENA0 with 3068 fanout uses global clock CLKCTRL_G4
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Info (11162): ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 with 3025 fanout uses global clock CLKCTRL_G3
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Info (12525): This signal is driven by core routing -- it may be moved during placement to reduce routing delays
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Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
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Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
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Info (332104): Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'
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Info (332104): Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'
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Info (332104): Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'
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Info (332104): Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'
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Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.
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Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.
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Info (332098): Cell: A_SPW_TOP|SPW|RX|always3~0 from: dataa to: combout
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Info (332098): Cell: A_SPW_TOP|SPW|RX|comb from: dataa to: combout
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Info (332098): Cell: m_x|always3~0 from: dataa to: combout
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Info (332098): Cell: m_x|comb from: datab to: combout
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Info (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457
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Info (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457
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Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclk
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Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclk
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Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkout
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Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkout
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Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclk
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Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclk
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Info (332152): The following assignments are ignored by the derive_clock_uncertainty command
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Info (332152): The following assignments are ignored by the derive_clock_uncertainty command
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Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
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Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
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Info (332111): Found 7 clocks
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Info (332111): Found 7 clocks
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Info (332111): Period Clock Name
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Info (332111): Period Clock Name
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Info (332111): ======== ============
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Info (332111): ======== ============
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Info (332111): 4.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i
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Info (332111): 10.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i
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Info (332111): 3.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i
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Info (332111): 2.500 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i
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Info (332111): 3.000 din_a
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Info (332111): 4.000 din_a
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Info (332111): 10.000 FPGA_CLK1_50
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Info (332111): 20.000 FPGA_CLK1_50
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Info (332111): 3.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e
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Info (332111): 4.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e
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Info (332111): 2.500 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
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Info (332111): 2.500 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
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Info (332111): 2.500 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]
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Info (332111): 2.500 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]
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Info (176233): Starting register packing
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Info (176233): Starting register packing
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Info (176222): Fitter will not automatically pack the registers into I/Os.
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Info (176221): The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os.
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Info (176235): Finished register packing
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Info (176235): Finished register packing
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Extra Info (176219): No registers were packed into other blocks
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Extra Info (176218): Packed 5 registers into blocks of type I/O output buffer
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Extra Info (176220): Created 5 register duplicates
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Info (223000): Starting Vectorless Power Activity Estimation
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Info (223000): Starting Vectorless Power Activity Estimation
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Info (223001): Completed Vectorless Power Activity Estimation
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Info (223001): Completed Vectorless Power Activity Estimation
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Info (11798): Fitter preparation operations ending: elapsed time is 00:00:16
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Info (128000): Starting physical synthesis optimizations for speed
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Warning (170136): Design uses Placement Effort Multiplier = 90.0. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt.
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Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
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Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 662 ps
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Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
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Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
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Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:09
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Info (176233): Starting register packing
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Info (176235): Finished register packing
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Extra Info (176219): No registers were packed into other blocks
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Info (11798): Fitter preparation operations ending: elapsed time is 00:00:30
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Warning (170136): Design uses Placement Effort Multiplier = 4.0. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt.
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Info (170189): Fitter placement preparation operations beginning
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Info (170189): Fitter placement preparation operations beginning
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Info (223000): Starting Vectorless Power Activity Estimation
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Info (223000): Starting Vectorless Power Activity Estimation
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Info (223001): Completed Vectorless Power Activity Estimation
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Info (223001): Completed Vectorless Power Activity Estimation
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Info (14951): The Fitter is using Advanced Physical Optimization.
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Info (14951): The Fitter is using Advanced Physical Optimization.
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Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:28
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Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:35
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Info (223000): Starting Vectorless Power Activity Estimation
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Info (223000): Starting Vectorless Power Activity Estimation
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Info (223001): Completed Vectorless Power Activity Estimation
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Info (223001): Completed Vectorless Power Activity Estimation
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Info (170191): Fitter placement operations beginning
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Info (170191): Fitter placement operations beginning
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Info (170137): Fitter placement was successful
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Info (170137): Fitter placement was successful
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Info (170192): Fitter placement operations ending: elapsed time is 00:01:55
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Info (170192): Fitter placement operations ending: elapsed time is 00:00:58
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Info (170193): Fitter routing operations beginning
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Info (170193): Fitter routing operations beginning
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Info (223000): Starting Vectorless Power Activity Estimation
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Info (223000): Starting Vectorless Power Activity Estimation
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Info (223001): Completed Vectorless Power Activity Estimation
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Info (223001): Completed Vectorless Power Activity Estimation
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Info (170195): Router estimated average interconnect usage is 3% of the available device resources
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Info (170195): Router estimated average interconnect usage is 4% of the available device resources
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Info (170196): Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X11_Y24 to location X22_Y36
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Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11
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Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
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Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
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Info (170200): Optimizations that may affect the design's timing were skipped
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Info (170194): Fitter routing operations ending: elapsed time is 00:01:16
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Info (170194): Fitter routing operations ending: elapsed time is 00:00:40
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Info (11888): Total time spent on timing analysis during the Fitter is 27.50 seconds.
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Info (11888): Total time spent on timing analysis during the Fitter is 16.50 seconds.
|
Info (334003): Started post-fitting delay annotation
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Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:05
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Info (334004): Delay annotation completed successfully
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Info (334003): Started post-fitting delay annotation
|
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Info (334004): Delay annotation completed successfully
|
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Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:38
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Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
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Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
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Info (144001): Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg
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Info (144001): Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg
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Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings
|
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings
|
Info: Peak virtual memory: 2064 megabytes
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Info: Peak virtual memory: 2473 megabytes
|
Info: Processing ended: Fri Sep 15 08:17:51 2017
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Info: Processing ended: Mon Feb 5 00:57:20 2018
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Info: Elapsed time: 00:04:44
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Info: Elapsed time: 00:05:09
|
Info: Total CPU time (on all processors): 00:08:19
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Info: Total CPU time (on all processors): 00:08:50
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+----------------------------+
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+----------------------------+
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; Fitter Suppressed Messages ;
|
; Fitter Suppressed Messages ;
|
+----------------------------+
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+----------------------------+
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