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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [ulight_fifo.qsys] - Diff between revs 32 and 40

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Rev 32 Rev 40
Line 347... Line 347...
 
 
   name="write_en_tx_external_connection"
   name="write_en_tx_external_connection"
   internal="write_en_tx.external_connection"
   internal="write_en_tx.external_connection"
   type="conduit"
   type="conduit"
   dir="end" />
   dir="end" />
 
 
  
  
  
  
  
  
  
  
  
  
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Line 384... Line 384...
  
  
 
 
 
 
   name="counter_rx_fifo"
   name="counter_rx_fifo"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 402... Line 402...
  
  
 
 
 
 
   name="counter_tx_fifo"
   name="counter_tx_fifo"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 420... Line 420...
  
  
 
 
 
 
   name="data_flag_rx"
   name="data_flag_rx"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 435... Line 435...
  
  
  
  
  
  
  
  
 
 
 
 
  
  
  
  
  
  
  
  
  
  
Line 452... Line 452...
  
  
 
 
 
 
   name="data_read_en_rx"
   name="data_read_en_rx"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 470... Line 470...
  
  
 
 
 
 
   name="fifo_empty_rx_status"
   name="fifo_empty_rx_status"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 488... Line 488...
  
  
 
 
 
 
   name="fifo_empty_tx_status"
   name="fifo_empty_tx_status"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 506... Line 506...
  
  
 
 
 
 
   name="fifo_full_rx_status"
   name="fifo_full_rx_status"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 524... Line 524...
  
  
 
 
 
 
   name="fifo_full_tx_status"
   name="fifo_full_tx_status"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 539... Line 539...
  
  
  
  
  
  
  
  
 
 
 
 
  
  
  
  
  
  
  
  
  
  
Line 553... Line 553...
  
  
  
  
  
  
  
  
 
 
 
 
  
  
  
  
  
  
  
  
  
  
Line 1035... Line 1035...
  
  
  
  
  
  
  
  
  {320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}
  {320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}
  
  
  
  
  
  
  
  
  
  
  
  
  
  
Line 1086... Line 1086...
  
  
 
 
 
 
   name="led_pio_test"
   name="led_pio_test"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 1104... Line 1104...
  
  
 
 
 
 
   name="link_disable"
   name="link_disable"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
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Line 1251... Line 1251...
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
Line 1331... Line 1331...
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  Automatic Switchover
  Automatic Switchover
  
  
 
 
 
 
   name="timecode_ready_rx"
   name="timecode_ready_rx"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 1357... Line 1357...
  
  
 
 
 
 
   name="timecode_rx"
   name="timecode_rx"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 1375... Line 1375...
  
  
 
 
 
 
   name="timecode_tx_data"
   name="timecode_tx_data"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 1393... Line 1393...
  
  
 
 
 
 
   name="timecode_tx_enable"
   name="timecode_tx_enable"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 1411... Line 1411...
  
  
 
 
 
 
   name="timecode_tx_ready"
   name="timecode_tx_ready"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 1429... Line 1429...
  
  
 
 
 
 
   name="write_data_fifo_tx"
   name="write_data_fifo_tx"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 1447... Line 1447...
  
  
 
 
 
 
   name="write_en_tx"
   name="write_en_tx"
   kind="altera_avalon_pio"
   kind="altera_avalon_pio"
   version="17.0"
   version="17.1"
   enabled="1">
   enabled="1">
  
  
  
  
  
  
  
  
Line 1464... Line 1464...
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="led_pio_test.s1">
   end="led_pio_test.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="timecode_rx.s1">
   end="timecode_rx.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="timecode_ready_rx.s1">
   end="timecode_ready_rx.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="data_flag_rx.s1">
   end="data_flag_rx.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="data_read_en_rx.s1">
   end="data_read_en_rx.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="fifo_full_rx_status.s1">
   end="fifo_full_rx_status.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="fifo_empty_rx_status.s1">
   end="fifo_empty_rx_status.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="link_start.s1">
   end="link_start.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="auto_start.s1">
   end="auto_start.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="link_disable.s1">
   end="link_disable.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="write_data_fifo_tx.s1">
   end="write_data_fifo_tx.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="write_en_tx.s1">
   end="write_en_tx.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="fifo_full_tx_status.s1">
   end="fifo_full_tx_status.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="fifo_empty_tx_status.s1">
   end="fifo_empty_tx_status.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="timecode_tx_data.s1">
   end="timecode_tx_data.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="timecode_tx_enable.s1">
   end="timecode_tx_enable.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="timecode_tx_ready.s1">
   end="timecode_tx_ready.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="data_info.s1">
   end="data_info.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="clock_sel.s1">
   end="clock_sel.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="fsm_info.s1">
   end="fsm_info.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="counter_tx_fifo.s1">
   end="counter_tx_fifo.s1">
  
  
  
  
  
  
 
 
 
 
   kind="avalon"
   kind="avalon"
   version="17.0"
   version="17.1"
   start="hps_0.h2f_axi_master"
   start="hps_0.h2f_axi_master"
   end="counter_rx_fifo.s1">
   end="counter_rx_fifo.s1">
  
  
  
  
  
  
 
 
 
 
 
 
 
 
   kind="clock"
   kind="clock"
   version="17.0"
   version="17.1"
   start="clk_0.clk"
   start="clk_0.clk"
   end="timecode_ready_rx.clk" />
   end="timecode_ready_rx.clk" />
 
 
 
 
   kind="clock"
   kind="clock"
   version="17.0"
   version="17.1"
   start="clk_0.clk"
   start="clk_0.clk"
   end="data_read_en_rx.clk" />
   end="fifo_empty_rx_status.clk" />
 
 
 
 
 
 
 
 
 
 
 
 
   kind="clock"
   kind="clock"
   version="17.0"
   version="17.1"
   start="clk_0.clk"
   start="clk_0.clk"
   end="fifo_full_rx_status.clk" />
   end="timecode_tx_data.clk" />
 
 
 
 
   kind="clock"
   kind="clock"
   version="17.0"
   version="17.1"
   start="clk_0.clk"
   start="clk_0.clk"
   end="fifo_empty_rx_status.clk" />
   end="timecode_tx_ready.clk" />
 
 
 
 
 
 
 
 
   kind="clock"
   kind="clock"
   version="17.0"
   version="17.1"
   start="clk_0.clk"
   start="clk_0.clk"
   end="write_data_fifo_tx.clk" />
   end="counter_tx_fifo.clk" />
 
 
 
 
   kind="clock"
   kind="clock"
   version="17.0"
   version="17.1"
   start="clk_0.clk"
   start="clk_0.clk"
   end="fifo_full_tx_status.clk" />
   end="counter_rx_fifo.clk" />
 
 
   kind="clock"
   kind="clock"
   version="17.0"
   version="17.1"
   start="clk_0.clk"
   start="clk_0.clk"
   end="fifo_empty_tx_status.clk" />
   end="write_data_fifo_tx.clk" />
 
 
   kind="clock"
   kind="clock"
   version="17.0"
   version="17.1"
   start="clk_0.clk"
   start="clk_0.clk"
   end="timecode_tx_data.clk" />
   end="timecode_tx_enable.clk" />
 
 
   kind="clock"
   kind="clock"
   version="17.0"
   version="17.1"
   start="clk_0.clk"
   start="clk_0.clk"
   end="timecode_tx_enable.clk" />
   end="fifo_full_tx_status.clk" />
 
 
   kind="clock"
   kind="clock"
   version="17.0"
   version="17.1"
   start="clk_0.clk"
   start="clk_0.clk"
   end="timecode_tx_ready.clk" />
   end="fifo_full_rx_status.clk" />
 
 
 
 
 
 
 
 
   kind="clock"
   kind="clock"
   version="17.0"
   version="17.1"
   start="clk_0.clk"
   start="clk_0.clk"
   end="counter_tx_fifo.clk" />
   end="data_read_en_rx.clk" />
 
 
   kind="clock"
   kind="clock"
   version="17.0"
   version="17.1"
   start="clk_0.clk"
   start="clk_0.clk"
   end="counter_rx_fifo.clk" />
   end="fifo_empty_tx_status.clk" />
 
 
 
 
 
 
   kind="clock"
   kind="clock"
   version="17.0"
   version="17.1"
   start="clk_0.clk"
   start="clk_0.clk"
   end="hps_0.h2f_axi_clock" />
   end="hps_0.h2f_axi_clock" />
 
 
 
 
 
 
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="led_pio_test.reset" />
   end="led_pio_test.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="timecode_rx.reset" />
   end="timecode_rx.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="timecode_ready_rx.reset" />
   end="timecode_ready_rx.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="data_flag_rx.reset" />
   end="data_flag_rx.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="data_read_en_rx.reset" />
   end="data_read_en_rx.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="fifo_full_rx_status.reset" />
   end="fifo_full_rx_status.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="fifo_empty_rx_status.reset" />
   end="fifo_empty_rx_status.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="link_start.reset" />
   end="link_start.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="auto_start.reset" />
   end="auto_start.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="link_disable.reset" />
   end="link_disable.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="write_data_fifo_tx.reset" />
   end="write_data_fifo_tx.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="write_en_tx.reset" />
   end="write_en_tx.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="fifo_full_tx_status.reset" />
   end="fifo_full_tx_status.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="fifo_empty_tx_status.reset" />
   end="fifo_empty_tx_status.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="timecode_tx_data.reset" />
   end="timecode_tx_data.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="timecode_tx_enable.reset" />
   end="timecode_tx_enable.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="timecode_tx_ready.reset" />
   end="timecode_tx_ready.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="data_info.reset" />
   end="data_info.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="clock_sel.reset" />
   end="clock_sel.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="fsm_info.reset" />
   end="fsm_info.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="counter_tx_fifo.reset" />
   end="counter_tx_fifo.reset" />
 
 
   kind="reset"
   kind="reset"
   version="17.0"
   version="17.1"
   start="clk_0.clk_reset"
   start="clk_0.clk_reset"
   end="counter_rx_fifo.reset" />
   end="counter_rx_fifo.reset" />
 
 
 
 
 
 

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