| Line 43... |
Line 43... |
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output rx_got_bit,
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output rx_got_bit,
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output rx_got_null,
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output rx_got_null,
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output rx_got_nchar,
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output rx_got_nchar,
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output rx_got_time_code,
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output rx_got_time_code,
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output rx_got_fct,
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output reg rx_got_fct,
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output reg [8:0] rx_data_flag,
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output reg [8:0] rx_data_flag,
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output reg rx_buffer_write,
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output reg rx_buffer_write,
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output reg [7:0] rx_time_out,
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output reg [7:0] rx_time_out,
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| Line 86... |
Line 86... |
reg last_was_control;
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reg last_was_control;
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reg last_was_data;
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reg last_was_data;
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reg last_was_timec;
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reg last_was_timec;
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reg [3:0] control;
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reg [3:0] control;
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reg [3:0] control_r;
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reg [9:0] data;
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reg [9:0] data;
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reg [9:0] timecode;
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reg [9:0] timecode;
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reg [3:0] control_l_r;
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reg [3:0] control_l_r;
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reg [9:0] data_l_r;
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reg [9:0] data_l_r;
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reg [9:0] dta_timec;
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reg parity_error;
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reg parity_error;
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wire check_c_d;
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wire check_c_d;
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reg rx_data_take;
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reg rx_data_take;
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reg first_time;
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//CLOCK RECOVERY
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//CLOCK RECOVERY
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assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
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assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
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assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0;
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assign negedge_clk = (!first_time)?1'b0:(!(rx_din ^ rx_sin))?1'b1:1'b0;
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assign check_c_d = ((is_control & counter_neg == 5'd2) == 1'b1 | (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 | (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;
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assign check_c_d = ((is_control & counter_neg == 5'd2) == 1'b1 | (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 | (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;
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assign rx_got_null = (control_l_r[2:0] == 3'd7 & control[2:0] == 3'd4)?1'b1:1'b0;
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assign rx_got_null = (control_l_r[2:0] == 3'd7 & control[2:0] == 3'd4)?1'b1:1'b0;
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assign rx_got_fct = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0;
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//assign rx_got_fct = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0;
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assign rx_got_bit = (posedge_clk)?1'b1:1'b0;
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assign rx_got_bit = (posedge_clk)?1'b1:1'b0;
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assign rx_error = parity_error;
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assign rx_error = parity_error;
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| Line 126... |
Line 131... |
bit_d_1 <= 1'b0;
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bit_d_1 <= 1'b0;
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bit_d_3 <= 1'b0;
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bit_d_3 <= 1'b0;
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bit_d_5 <= 1'b0;
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bit_d_5 <= 1'b0;
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bit_d_7 <= 1'b0;
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bit_d_7 <= 1'b0;
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bit_d_9 <= 1'b0;
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bit_d_9 <= 1'b0;
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first_time <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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bit_c_1 <= rx_din;
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bit_c_1 <= rx_din;
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bit_c_3 <= bit_c_1;
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bit_c_3 <= bit_c_1;
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| Line 137... |
Line 144... |
bit_d_1 <= rx_din;
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bit_d_1 <= rx_din;
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bit_d_3 <= bit_d_1;
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bit_d_3 <= bit_d_1;
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bit_d_5 <= bit_d_3;
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bit_d_5 <= bit_d_3;
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bit_d_7 <= bit_d_5;
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bit_d_7 <= bit_d_5;
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bit_d_9 <= bit_d_7;
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bit_d_9 <= bit_d_7;
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first_time <= 1'b1;
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end
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end
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end
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end
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always@(posedge negedge_clk or negedge rx_resetn)
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always@(posedge negedge_clk or negedge rx_resetn)
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| Line 155... |
Line 162... |
bit_d_0 <= 1'b0;
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bit_d_0 <= 1'b0;
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bit_d_2 <= 1'b0;
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bit_d_2 <= 1'b0;
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bit_d_4 <= 1'b0;
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bit_d_4 <= 1'b0;
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bit_d_6 <= 1'b0;
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bit_d_6 <= 1'b0;
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bit_d_8 <= 1'b0;
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bit_d_8 <= 1'b0;
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is_control <= 1'b0;
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is_data <= 1'b0;
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counter_neg <= 5'd0;
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end
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end
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else
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else
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begin
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begin
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bit_c_0 <= rx_din;
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bit_c_0 <= rx_din;
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bit_c_2 <= bit_c_0;
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bit_c_2 <= bit_c_0;
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bit_d_0 <= rx_din;
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bit_d_0 <= rx_din;
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bit_d_2 <= bit_d_0;
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bit_d_2 <= bit_d_0;
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bit_d_4 <= bit_d_2;
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bit_d_4 <= bit_d_2;
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bit_d_6 <= bit_d_4;
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bit_d_6 <= bit_d_4;
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bit_d_8 <= bit_d_6;
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bit_d_8 <= bit_d_6;
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end
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end
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always@(*)
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begin
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rx_got_fct = 1'b0;
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if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && check_c_d)
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begin
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rx_got_fct = 1'b1;
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end
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end
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always@(*)
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begin
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dta_timec = 10'd0;
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control_r = 4'd0;
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if(counter_neg == 5'd2)
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begin
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control_r = {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
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end
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else if(counter_neg == 5'd5)
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begin
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dta_timec = {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
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end
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end
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always@(posedge negedge_clk or negedge rx_resetn)
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begin
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if(!rx_resetn)
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begin
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is_control <= 1'b0;
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is_data <= 1'b0;
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counter_neg <= 5'd0;
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end
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else
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begin
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if(counter_neg == 5'd1)
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if(counter_neg == 5'd1)
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begin
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begin
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if(bit_c_0)
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if(bit_c_0)
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begin
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begin
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is_control <= 1'b1;
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is_control <= 1'b1;
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| Line 221... |
Line 261... |
end
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end
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end
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end
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end
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end
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end
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end
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always@(*)
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always@(*)
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begin
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begin
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parity_error = 1'b0;
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parity_error = 1'b0;
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| Line 282... |
Line 323... |
always@(posedge check_c_d or negedge rx_resetn )
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always@(posedge check_c_d or negedge rx_resetn )
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begin
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begin
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if(!rx_resetn)
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if(!rx_resetn)
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begin
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begin
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control <= 4'd0;
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control_l_r <= 4'd0;
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control_l_r <= 4'd0;
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control <= 4'd0;
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data <= 10'd0;
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data <= 10'd0;
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data_l_r <= 10'd0;
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data_l_r <= 10'd0;
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rx_data_flag <= 9'd0;
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rx_data_flag <= 9'd0;
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rx_buffer_write <= 1'b0;
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rx_buffer_write <= 1'b0;
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rx_data_take <= 1'b0;
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rx_data_take <= 1'b0;
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| Line 310... |
Line 351... |
begin
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begin
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rx_buffer_write <= rx_data_take;
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rx_buffer_write <= rx_data_take;
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rx_data_flag <= data[8:0];
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rx_data_flag <= data[8:0];
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rx_time_out <= timecode;
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rx_time_out <= timecode[7:0];
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if((control[2:0] != 3'd7 & is_data) == 1'b1)
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if((control_r[2:0] != 3'd7 & is_data) == 1'b1)
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begin
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begin
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data <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
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data <= dta_timec;
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data_l_r <= data;
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data_l_r <= data;
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rx_data_take <= 1'b1;
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rx_data_take <= 1'b1;
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rx_tick_out <= 1'b0;
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rx_tick_out <= 1'b0;
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| Line 328... |
Line 369... |
last_is_timec <=1'b0;
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last_is_timec <=1'b0;
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last_was_control <= last_is_control;
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last_was_control <= last_is_control;
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last_was_data <= last_is_data ;
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last_was_data <= last_is_data ;
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last_was_timec <= last_is_timec;
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last_was_timec <= last_is_timec;
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end
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end
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else if((control[2:0] == 3'd7 & is_data) == 1'b1)
|
else if((control_r[2:0] == 3'd7 && is_data) == 1'b1)
|
begin
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begin
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|
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timecode <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
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timecode <= dta_timec;
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rx_tick_out <= 1'b1;
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rx_tick_out <= 1'b1;
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rx_data_take <= 1'b0;
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rx_data_take <= 1'b0;
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|
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last_is_control <= 1'b0;
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last_is_control <= 1'b0;
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last_is_data <= 1'b0;
|
last_is_data <= 1'b0;
|
last_is_timec <= 1'b1;
|
last_is_timec <= 1'b1;
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last_was_control <= last_is_control;
|
last_was_control <= last_is_control;
|
last_was_data <= last_is_data ;
|
last_was_data <= last_is_data ;
|
last_was_timec <= last_is_timec;
|
last_was_timec <= last_is_timec;
|
end
|
end
|
else if({bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd6 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd13 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd5 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd15 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd7 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd4 | | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd12)
|
else if(control_r == 4'd6 || control_r == 4'd13 || control_r == 4'd5 || control_r == 4'd15 || control_r == 4'd7 || control_r == 4'd4 || control_r == 4'd12)
|
begin
|
begin
|
|
|
control <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
|
control <= control_r;
|
control_l_r <= control[3:0];
|
control_l_r <= control[3:0];
|
|
|
if((control[2:0] == 3'd6 & is_control) == 1'b1 )
|
if((control_r[2:0] == 3'd6 & is_control) == 1'b1 )
|
begin
|
begin
|
data <= 10'b0100000001;
|
data <= 10'b0100000001;
|
rx_data_take <= 1'b1;
|
rx_data_take <= 1'b1;
|
end
|
end
|
else if( (control[2:0] == 3'd5 & is_control) == 1'b1 )
|
else if( (control_r[2:0] == 3'd5 & is_control) == 1'b1 )
|
begin
|
begin
|
data <= 10'b0100000000;
|
data <= 10'b0100000000;
|
rx_data_take <= 1'b1;
|
rx_data_take <= 1'b1;
|
end
|
end
|
else
|
else
|
