//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//FILE NAME :
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//DEPARTMENT : IC Design / Verification
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH [32,16] : width of the DATA : 32:
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//Reset Strategy :
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//Clock Domains :
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//Critical Timing :
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//Test Features :
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//Asynchronous I/F :
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//Scan Methodology :
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//Instantiations :
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//Synthesizable (y/n) :
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//Other :
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//-FHDR------------------------------------------------------------------------
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#include <systemc.h>
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#include <systemc.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <vector>
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#include <vector>
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#include <string>
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#include <string>
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#include <stdlib.h>
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#include <stdlib.h>
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#include <gtkmm.h>
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#include <gtkmm.h>
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#include <random>
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#include <random>
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#include <boost/thread.hpp>
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#include <boost/thread.hpp>
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using namespace std;
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using namespace std;
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using namespace Gtk;
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using namespace Gtk;
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using namespace boost;
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using namespace boost;
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#include "../gladicapi/data_recorder.h"
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#include "../gladicapi/data_recorder.h"
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#include "../gladicapi/data_check.h"
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#include "../gladicapi/data_check.h"
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bool enable_null;
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bool enable_fct;
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bool enable_time_code;
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bool enable_n_char;
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bool EEP_EOP;
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bool EEP_EOP;
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unsigned int finish = 0;
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unsigned int finish = 0;
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bool link_start = false;
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bool link_start = false;
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bool link_disable = false;
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bool link_disable = false;
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bool auto_start = false;
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bool auto_start = false;
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//systemc and verilog
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//systemc and verilog
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bool global_reset = false;
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bool global_reset = false;
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//verilog variables
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//verilog variables
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bool verilog_link_start = false;
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bool verilog_link_start = false;
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bool verilog_link_disable = false;
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bool verilog_link_disable = false;
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bool verilog_auto_start = false;
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bool verilog_auto_start = false;
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int frquency_nano_second = 500;
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int frquency_nano_second = 500;
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vector<string> data_col_store;
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vector<string> data_col_store;
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data_recorder *REC_TX_SPW;
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data_recorder *REC_TX_SPW;
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data_check *COMPARE_SPW;
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data_check *COMPARE_SPW;
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vector<string> data_col_store0;
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vector<string> data_col_store0;
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data_recorder *REC_TX_SPWSC;
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data_recorder *REC_TX_SPWSC;
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data_check *COMPARE_SPW_RX;
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data_check *COMPARE_SPW_RX;
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unsigned long int a = 0;
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unsigned long int a = 0;
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int clock_systemc = 2;
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int clock_systemc = 2;
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//send data systemC
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//send data systemC
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bool start_send_data_verilog = false;
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bool start_send_data_verilog = false;
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bool enable_time_code_verilog = false;
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bool enable_time_code_verilog = false;
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bool start_send_data = false;
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bool start_send_data = false;
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bool start_tick_data = false;
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bool start_tick_data = false;
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vector<sc_uint<9> > data_generated_sc;
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vector<sc_uint<9> > data_generated_sc;
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sc_uint<9> intermediate_systemc;
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sc_uint<9> intermediate_systemc;
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sc_uint<9> intermediate_sc;
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sc_uint<9> intermediate_sc;
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unsigned int data_iteration_sc_aux = 0;
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unsigned int data_iteration_sc_aux = 0;
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unsigned int data_iteration_sc = 0;
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unsigned int data_iteration_sc = 0;
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vector<sc_uint<9> > data_generated_verilog;
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vector<sc_uint<9> > data_generated_verilog;
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sc_uint<9> intermediate;
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sc_uint<9> intermediate;
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sc_uint<9> intermediate_verilog;
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sc_uint<9> intermediate_verilog;
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unsigned int data_iteration = 0;
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unsigned int data_iteration = 0;
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unsigned int data_iteration_vlog = 0;
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unsigned int data_iteration_vlog = 0;
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sc_uint<9> intermediate_data;
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sc_uint<9> intermediate_data;
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void data_rx_sc_o(unsigned int type_char, sc_uint<4> control, sc_uint<4> last_control_sys , sc_uint<10> data , sc_uint<10> timecode_sys);
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#include "top_spw.h"
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#include "top_spw.h"
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//Data generation
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//Data generation
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unsigned long int max_data = 100;
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unsigned long int max_data = 255;
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std::random_device rd;
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std::random_device rd;
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std::uniform_int_distribution<unsigned long int> data_in(0,255);
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std::uniform_int_distribution<unsigned long int> data_in(0,255);
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std::uniform_int_distribution<unsigned long int> nchar(1,max_data-1);//eop-eep
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std::uniform_int_distribution<unsigned long int> nchar(1,max_data);//eop-eep
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class sc_TOP_SPW;
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class sc_TOP_SPW;
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SC_MODULE(sc_TOP_SPW)
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SC_MODULE(sc_TOP_SPW)
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{
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{
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sc_clock CLOCK;
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sc_clock CLOCK;
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sc_signal<bool> RESET;
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sc_signal<bool> RESET;
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sc_signal<bool> LINK_START;
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sc_signal<bool> LINK_START;
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sc_signal<bool> LINK_DISABLE;
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sc_signal<bool> LINK_DISABLE;
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sc_signal<bool> AUTO_START;
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sc_signal<bool> AUTO_START;
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sc_signal<sc_uint<4> > FSM_SPW_OUT;
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sc_signal<sc_uint<4> > FSM_SPW_OUT;
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sc_signal<sc_uint<4> > FSM_TX;
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sc_signal<sc_uint<4> > FSM_TX;
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sc_signal<sc_uint<10> > CLOCK_GEN;
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sc_signal<sc_uint<10> > CLOCK_GEN;
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sc_signal<bool> E_SEND_DATA;
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sc_signal<bool> E_SEND_DATA;
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//sc_signal<bool> TICKIN_TX;
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//sc_signal<sc_uint<8> > TIMEIN_CONTROL_FLAG_TX;
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//sc_signal<bool> TXWRITE_TX;
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//sc_signal<sc_uint<9> > TXDATA_FLAGCTRL_TX;
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//sc_signal<bool> READY_TX;
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//sc_signal<bool> READY_TICK;
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sc_signal<bool> BUFFER_READY;
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sc_signal<bool> BUFFER_READY;
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sc_signal<sc_uint<9> > DATARX_FLAG;
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sc_signal<sc_uint<9> > DATARX_FLAG;
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sc_signal<bool> BUFFER_WRITE;
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sc_signal<bool> BUFFER_WRITE;
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sc_signal<sc_uint<8> > TIME_OUT;
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sc_signal<sc_uint<8> > TIME_OUT;
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sc_signal<bool> TICK_OUT;
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sc_signal<bool> TICK_OUT;
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sc_signal<bool> CONTROL_FLAG_OUT;
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sc_signal<bool> CONTROL_FLAG_OUT;
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sc_signal<uint> DOUT;
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sc_signal<uint> DOUT;
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sc_signal<uint> SOUT;
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sc_signal<uint> SOUT;
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sc_signal<uint> DIN;
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sc_signal<uint> DIN;
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sc_signal<uint> SIN;
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sc_signal<uint> SIN;
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sc_TOP DUT;
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sc_TOP DUT;
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SC_CTOR(sc_TOP_SPW) :CLOCK("CLOCK",20,SC_NS),
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SC_CTOR(sc_TOP_SPW) :CLOCK("CLOCK",20,SC_NS),
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RESET("RESET"),
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RESET("RESET"),
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LINK_DISABLE("LINK_DISABLE"),
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LINK_DISABLE("LINK_DISABLE"),
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LINK_START("LINK_START"),
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LINK_START("LINK_START"),
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AUTO_START("AUTO_START"),
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AUTO_START("AUTO_START"),
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FSM_SPW_OUT("FSM_SPW_OUT"),
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FSM_SPW_OUT("FSM_SPW_OUT"),
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CLOCK_GEN("CLOCK_GEN"),
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CLOCK_GEN("CLOCK_GEN"),
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E_SEND_DATA("E_SEND_DATA"),
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E_SEND_DATA("E_SEND_DATA"),
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//TICKIN_TX("TICKIN_TX"),
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//TIMEIN_CONTROL_FLAG_TX("TIMEIN_CONTROL_FLAG_TX"),
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//TXWRITE_TX("TXWRITE_TX"),
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//TXDATA_FLAGCTRL_TX("TXDATA_FLAGCTRL_TX"),
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//READY_TX("READY_TX"),
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//READY_TICK("READY_TICK"),
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DOUT("DOUT"),
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DOUT("DOUT"),
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SOUT("SOUT"),
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SOUT("SOUT"),
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FSM_TX("FSM_TX"),
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FSM_TX("FSM_TX"),
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DIN("DIN"),
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DIN("DIN"),
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SIN("SIN"),
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SIN("SIN"),
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BUFFER_READY("BUFFER_READY"),
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BUFFER_READY("BUFFER_READY"),
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DATARX_FLAG("DATARX_FLAG"),
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DATARX_FLAG("DATARX_FLAG"),
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BUFFER_WRITE("BUFFER_WRITE"),
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BUFFER_WRITE("BUFFER_WRITE"),
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TIME_OUT("TIME_OUT"),
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TIME_OUT("TIME_OUT"),
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TICK_OUT("TICK_OUT"),
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TICK_OUT("TICK_OUT"),
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CONTROL_FLAG_OUT("CONTROL_FLAG_OUT"),
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CONTROL_FLAG_OUT("CONTROL_FLAG_OUT"),
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DUT("DUT") {
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DUT("DUT") {
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DUT.CLOCK(CLOCK);
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DUT.CLOCK(CLOCK);
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DUT.RESET(RESET);
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DUT.RESET(RESET);
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DUT.LINK_DISABLE(LINK_DISABLE);
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DUT.LINK_DISABLE(LINK_DISABLE);
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DUT.AUTO_START(AUTO_START);
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DUT.AUTO_START(AUTO_START);
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DUT.LINK_START(LINK_START);
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DUT.LINK_START(LINK_START);
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DUT.FSM_SPW_OUT(FSM_SPW_OUT);
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DUT.FSM_SPW_OUT(FSM_SPW_OUT);
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DUT.CLOCK_GEN(CLOCK_GEN);
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DUT.CLOCK_GEN(CLOCK_GEN);
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DUT.E_SEND_DATA(E_SEND_DATA);
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DUT.E_SEND_DATA(E_SEND_DATA);
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//DUT.TICKIN_TX(TICKIN_TX);
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//DUT.TIMEIN_CONTROL_FLAG_TX(TIMEIN_CONTROL_FLAG_TX);
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//DUT.TXWRITE_TX(TXWRITE_TX);
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//DUT.TXDATA_FLAGCTRL_TX(TXDATA_FLAGCTRL_TX);
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DUT.FSM_TX(FSM_TX);
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DUT.FSM_TX(FSM_TX);
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//DUT.READY_TX(READY_TX);
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//DUT.READY_TICK(READY_TICK);
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DUT.DOUT(DOUT);
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DUT.DOUT(DOUT);
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DUT.SOUT(SOUT);
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DUT.SOUT(SOUT);
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DUT.DIN(DIN);
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DUT.DIN(DIN);
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DUT.SIN(SIN);
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DUT.SIN(SIN);
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DUT.BUFFER_READY(BUFFER_READY);
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DUT.BUFFER_READY(BUFFER_READY);
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DUT.DATARX_FLAG(DATARX_FLAG);
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DUT.DATARX_FLAG(DATARX_FLAG);
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DUT.BUFFER_WRITE(BUFFER_WRITE);
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DUT.BUFFER_WRITE(BUFFER_WRITE);
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DUT.TIME_OUT(TIME_OUT);
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DUT.TIME_OUT(TIME_OUT);
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DUT.TICK_OUT(TICK_OUT);
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DUT.TICK_OUT(TICK_OUT);
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DUT.CONTROL_FLAG_OUT(CONTROL_FLAG_OUT);
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DUT.CONTROL_FLAG_OUT(CONTROL_FLAG_OUT);
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cout << "SC_CTOR(sc_TOP_SPW)" << endl;
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cout << "SC_CTOR(sc_TOP_SPW)" << endl;
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}
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}
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};
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};
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Glib::RefPtr<Gtk::Builder> builder;
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Glib::RefPtr<Gtk::Builder> builder;
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Gtk::Window *window;
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Gtk::Window *window;
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Gtk::Button *BtnFinsihSimulation;
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Gtk::Button *BtnFinsihSimulation;
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Gtk::Button *BtnLinkEnable;
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Gtk::Button *BtnLinkEnable;
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Gtk::Button *BtnLinkDisable;
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Gtk::Button *BtnLinkDisable;
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Gtk::Button *BtnAutoStart;
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Gtk::Button *BtnAutoStart;
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Gtk::Button *BtnReset;
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Gtk::Button *BtnReset;
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Gtk::Button *BtnSpaceWireVerilog;
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Gtk::Button *BtnSpaceWireVerilog;
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Gtk::CheckButton *CheckbtnLinkEnable;
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Gtk::CheckButton *CheckbtnLinkEnable;
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Gtk::CheckButton *CheckbtnAutoStart;
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Gtk::CheckButton *CheckbtnAutoStart;
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Gtk::CheckButton *CheckbtnLinkDisable;
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Gtk::CheckButton *CheckbtnLinkDisable;
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//Execute test
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//Execute test
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Gtk::Button *BtnSimpleTest;
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Gtk::Button *BtnSimpleTest;
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Gtk::CheckButton *CheckBtnEop;
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Gtk::CheckButton *CheckBtnEop;
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Gtk::CheckButton *CheckBtnEep;
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Gtk::CheckButton *CheckBtnEep;
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Gtk::CheckButton *CheckBtnTimeCode;
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Gtk::CheckButton *CheckBtnTimeCode;
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//Generate data
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//Generate data
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Gtk::Button *BtnGenerationDataVerilog;
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Gtk::Button *BtnGenerationDataVerilog;
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Gtk::CheckButton *CheckBtnEopGenVerilog;
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Gtk::CheckButton *CheckBtnEopGenVerilog;
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Gtk::CheckButton *CheckBtnEepGenVerilog;
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Gtk::CheckButton *CheckBtnEepGenVerilog;
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Gtk::CheckButton *CheckBtnTimeCodeGenVerilog;
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Gtk::CheckButton *CheckBtnTimeCodeGenVerilog;
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Gtk::Button *BtnTxFrequency;
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Gtk::Button *BtnTxFrequency;
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Gtk::Entry *EntryFrequency;
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Gtk::Entry *EntryFrequency;
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Gtk::Button *BtnChangeFrequencyVerilog;
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Gtk::Button *BtnChangeFrequencyVerilog;
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Gtk::Entry *EntryFrequencyVerilog;
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Gtk::Entry *EntryFrequencyVerilog;
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Gtk::Button *BtnSendDataScTx;
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Gtk::Button *BtnSendDataScTx;
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Gtk::Button *BtnTimeCodeScTx;
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Gtk::Button *BtnTimeCodeScTx;
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Gtk::Button *BtnGenerateDataSc;
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Gtk::Button *BtnGenerateDataSc;
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Gtk::CheckButton *CheckBtnEepGenSystemC;
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Gtk::CheckButton *CheckBtnEepGenSystemC;
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Gtk::CheckButton *CheckBtnEopGenSystemC;
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Gtk::CheckButton *CheckBtnEopGenSystemC;
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Gtk::Label *lblStatus;
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Gtk::Label *lblStatus;
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sc_TOP_SPW *sn_top;
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sc_TOP_SPW *sn_top;
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extern "C" Control_SC* create_object()
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extern "C" Control_SC* create_object()
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{
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{
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return new Control_SC;
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return new Control_SC;
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}
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}
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extern "C" void destroy_object( Control_SC* object )
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extern "C" void destroy_object( Control_SC* object )
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{
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{
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delete object;
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delete object;
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}
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}
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/*GTKMM CONTROL*/
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/*GTKMM CONTROL*/
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void on_BtnFinsihSimulation_clicked()
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void on_BtnFinsihSimulation_clicked()
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{
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{
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cout<< "End Simulation" <<endl;
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cout<< "End Simulation" <<endl;
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Gtk::Main::quit();
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Gtk::Main::quit();
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finish = 1;
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finish = 1;
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REC_TX_SPW->endsimulation();
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REC_TX_SPW->endsimulation();
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REC_TX_SPWSC->endsimulation();
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REC_TX_SPWSC->endsimulation();
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}
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}
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void on_BtnLinkEnable_clicked()
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void on_BtnLinkEnable_clicked()
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{
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{
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link_start = !link_start;
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link_start = !link_start;
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}
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}
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void on_BtnLinkDisable_clicked()
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void on_BtnLinkDisable_clicked()
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{
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{
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link_disable = !link_disable;
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link_disable = !link_disable;
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}
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}
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void on_BtnAutoStart_clicked()
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void on_BtnAutoStart_clicked()
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{
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{
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auto_start = !auto_start;
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auto_start = !auto_start;
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}
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}
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void on_BtnReset_clicked()
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void on_BtnReset_clicked()
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{
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{
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global_reset = !global_reset;
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global_reset = !global_reset;
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}
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}
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void on_BtnSpaceWireVerilog_clicked()
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void on_BtnSpaceWireVerilog_clicked()
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{
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{
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if(!CheckbtnLinkEnable->get_active())
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if(!CheckbtnLinkEnable->get_active())
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{
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{
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verilog_link_start = false;
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verilog_link_start = false;
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lblStatus->set_text("LINKENABLE VERILOG IS OFF");
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lblStatus->set_text("LINKENABLE VERILOG IS OFF");
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}
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}
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if(!CheckbtnAutoStart->get_active())
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if(!CheckbtnAutoStart->get_active())
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{
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{
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verilog_auto_start = false;
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verilog_auto_start = false;
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lblStatus->set_text("AUTOSTART VERILOG IS OFF");
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lblStatus->set_text("AUTOSTART VERILOG IS OFF");
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}
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}
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if(!CheckbtnLinkDisable->get_active())
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if(!CheckbtnLinkDisable->get_active())
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{
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{
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verilog_link_disable = false;
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verilog_link_disable = false;
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lblStatus->set_text("AUTOSTART VERILOG IS OFF");
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lblStatus->set_text("AUTOSTART VERILOG IS OFF");
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}
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}
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if(CheckbtnLinkEnable->get_active())
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if(CheckbtnLinkEnable->get_active())
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{
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{
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verilog_link_start = true;
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verilog_link_start = true;
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lblStatus->set_text("LINKENABLE VERILOG IS ON");
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lblStatus->set_text("LINKENABLE VERILOG IS ON");
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}
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}
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if(CheckbtnAutoStart->get_active())
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if(CheckbtnAutoStart->get_active())
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{
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{
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verilog_auto_start = true;
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verilog_auto_start = true;
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lblStatus->set_text("AUTOSTART VERILOG IS ON");
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lblStatus->set_text("AUTOSTART VERILOG IS ON");
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}
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}
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if(CheckbtnLinkDisable->get_active())
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if(CheckbtnLinkDisable->get_active())
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{
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{
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verilog_link_disable = true;
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verilog_link_disable = true;
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lblStatus->set_text("LINKDISABLE VERILOG IS ON");
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lblStatus->set_text("LINKDISABLE VERILOG IS ON");
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}
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}
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}
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}
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void on_BtnSimpleTest_clicked()
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void on_BtnSimpleTest_clicked()
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{
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{
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if(CheckBtnEopGenVerilog->get_active())
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if(CheckBtnEopGenVerilog->get_active())
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{
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{
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start_send_data_verilog = true;
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start_send_data_verilog = true;
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}
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}
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else
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else
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{
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{
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start_send_data_verilog = false;
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start_send_data_verilog = false;
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}
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}
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if(CheckBtnTimeCodeGenVerilog->get_active())
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if(CheckBtnTimeCodeGenVerilog->get_active())
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{
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{
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enable_time_code_verilog = true;
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enable_time_code_verilog = true;
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}
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}
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else
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else
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{
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{
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enable_time_code_verilog = false;
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enable_time_code_verilog = false;
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}
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}
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/*
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data_generated.clear();
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data_iteration=0;
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data_iteration_vlog=0;
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if(CheckBtnEop->get_active())
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{
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for(int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
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{
|
|
if(cnt_max_data == 0 || cnt_max_data == max_data)
|
|
{
|
|
intermediate(8,8) = 1;
|
|
intermediate(7,0) = 0;
|
|
}else if(cnt_max_data > 0 && cnt_max_data < max_data)
|
|
{
|
|
intermediate(7,0) = data_in(rd);
|
|
intermediate(8,8) = 0;
|
|
}
|
|
data_generated.push_back(intermediate);
|
|
}
|
|
start_send_data_verilog = true;
|
|
}else if(CheckBtnEep->get_active())
|
|
{
|
|
for(int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
|
|
{
|
|
if(cnt_max_data == 0 || cnt_max_data == max_data)
|
|
{
|
|
intermediate(8,8) = 1;
|
|
intermediate(7,0) = 1;
|
|
}else if(cnt_max_data > 0 && cnt_max_data < max_data)
|
|
{
|
|
intermediate(7,0) = data_in(rd);
|
|
intermediate(8,8) = 0;
|
|
}
|
|
data_generated.push_back(intermediate);
|
|
}
|
|
intermediate(7,0) = 1;
|
|
intermediate(8,8) = 1;
|
|
data_generated[nchar(rd)] = intermediate;
|
|
start_send_data_verilog = true;
|
|
}
|
|
|
|
if(CheckBtnTimeCode->get_active())
|
|
{
|
|
enable_time_code_verilog = true;
|
|
}
|
|
*/
|
|
|
|
|
|
}
|
}
|
|
|
void on_BtnGenerationDataVerilog_clicked()
|
void on_BtnGenerationDataVerilog_clicked()
|
{
|
{
|
data_generated_verilog.clear();
|
data_generated_verilog.clear();
|
data_iteration=0;
|
data_iteration=0;
|
data_iteration_vlog=0;
|
data_iteration_vlog=0;
|
if(CheckBtnEopGenVerilog->get_active())
|
if(CheckBtnEopGenVerilog->get_active())
|
{
|
{
|
for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
|
for(int cnt_max_data = 0; cnt_max_data < max_data;cnt_max_data++)
|
{
|
|
if(cnt_max_data == 0 || cnt_max_data == max_data)
|
|
{
|
{
|
intermediate_verilog(8,8) = 1;
|
if(cnt_max_data >= 0 && cnt_max_data < max_data)
|
intermediate_verilog(7,0) = 0;
|
|
}else if(cnt_max_data > 0 && cnt_max_data < max_data)
|
|
{
|
{
|
intermediate_verilog(7,0) = data_in(rd);
|
intermediate_verilog(7,0) = data_in(rd);
|
intermediate_verilog(8,8) = 0;
|
intermediate_verilog(8,8) = 0;
|
}
|
|
data_generated_verilog.push_back(intermediate_verilog);
|
data_generated_verilog.push_back(intermediate_verilog);
|
}
|
}
|
|
intermediate_verilog=0;
|
|
|
|
}
|
|
|
|
intermediate_verilog(8,8) = 1;
|
|
intermediate_verilog(7,0) = 0;
|
|
|
|
data_generated_verilog.push_back(intermediate_verilog);
|
|
intermediate_verilog=0;
|
}else if(CheckBtnEepGenVerilog->get_active())
|
}else if(CheckBtnEepGenVerilog->get_active())
|
{
|
{
|
for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
|
for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
|
{
|
{
|
if(cnt_max_data == 0 || cnt_max_data == max_data)
|
if(cnt_max_data == 0 || cnt_max_data == max_data)
|
{
|
{
|
intermediate_verilog(8,8) = 1;
|
intermediate_verilog(8,8) = 1;
|
intermediate_verilog(7,0) = 1;
|
intermediate_verilog(7,0) = 1;
|
}else if(cnt_max_data > 0 && cnt_max_data < max_data)
|
}else if(cnt_max_data > 0 && cnt_max_data < max_data)
|
{
|
{
|
intermediate_verilog(7,0) = data_in(rd);
|
intermediate_verilog(7,0) = data_in(rd);
|
intermediate_verilog(8,8) = 0;
|
intermediate_verilog(8,8) = 0;
|
}
|
}
|
|
else
|
|
{
|
|
intermediate_verilog(7,0) = data_in(rd);
|
|
intermediate_verilog(8,8) = 0;
|
|
}
|
data_generated_verilog.push_back(intermediate_verilog);
|
data_generated_verilog.push_back(intermediate_verilog);
|
|
intermediate_verilog=0;
|
}
|
}
|
intermediate_verilog(7,0) = 1;
|
intermediate_verilog(7,0) = 1;
|
intermediate_verilog(8,8) = 1;
|
intermediate_verilog(8,8) = 1;
|
data_generated_verilog[nchar(rd)] = intermediate_verilog;
|
data_generated_verilog[nchar(rd)] = intermediate_verilog;
|
}
|
}
|
}
|
}
|
|
|
void on_BtnTxFrequency_clicked()
|
void on_BtnTxFrequency_clicked()
|
{
|
{
|
|
|
string aux = EntryFrequency->get_text();
|
string aux = EntryFrequency->get_text();
|
switch(atoi(aux.c_str()))
|
switch(atoi(aux.c_str()))
|
{
|
{
|
case 2:
|
case 2:
|
sn_top->CLOCK_GEN = 1;
|
sn_top->CLOCK_GEN = 1;
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 2MHz");
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 2MHz");
|
break;
|
break;
|
case 10:
|
case 10:
|
sn_top->CLOCK_GEN = 2;
|
sn_top->CLOCK_GEN = 2;
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 10MHz");
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 10MHz");
|
break;
|
break;
|
case 20:
|
case 20:
|
sn_top->CLOCK_GEN = 4;
|
sn_top->CLOCK_GEN = 4;
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 20MHz");
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 20MHz");
|
break;
|
break;
|
case 50:
|
case 50:
|
sn_top->CLOCK_GEN = 8;
|
sn_top->CLOCK_GEN = 8;
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 50MHz");
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 50MHz");
|
break;
|
break;
|
case 100:
|
case 100:
|
sn_top->CLOCK_GEN = 16;
|
sn_top->CLOCK_GEN = 16;
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 100MHz");
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 100MHz");
|
break;
|
break;
|
case 150:
|
case 150:
|
sn_top->CLOCK_GEN = 32;
|
sn_top->CLOCK_GEN = 32;
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 150MHz");
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 150MHz");
|
break;
|
break;
|
case 200:
|
case 200:
|
sn_top->CLOCK_GEN = 64;
|
sn_top->CLOCK_GEN = 64;
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 200MHz");
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 200MHz");
|
break;
|
break;
|
case 201:
|
case 201:
|
sn_top->CLOCK_GEN = 128;
|
sn_top->CLOCK_GEN = 128;
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 201MHz");
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 201MHz");
|
break;
|
break;
|
case 250:
|
case 250:
|
sn_top->CLOCK_GEN = 256;
|
sn_top->CLOCK_GEN = 256;
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 250MHz");
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 250MHz");
|
break;
|
break;
|
case 280:
|
case 280:
|
sn_top->CLOCK_GEN = 512;
|
sn_top->CLOCK_GEN = 512;
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 280MHz");
|
lblStatus->set_text("TX CLOCK SYSTEMC SET IN 280MHz");
|
break;
|
break;
|
}
|
}
|
|
|
}
|
}
|
|
|
void on_BtnTimeCodeScTx_clicked()
|
void on_BtnTimeCodeScTx_clicked()
|
{
|
{
|
start_tick_data = !start_tick_data;
|
start_tick_data = !start_tick_data;
|
if(start_tick_data)
|
if(start_tick_data)
|
{lblStatus->set_text("TIME CODE ENABLED ON TX SYSTEMC");}
|
{lblStatus->set_text("TIME CODE ENABLED ON TX SYSTEMC");}
|
else
|
else
|
{lblStatus->set_text("TIME CODE DISABLED ON TX SYSTEMC");}
|
{lblStatus->set_text("TIME CODE DISABLED ON TX SYSTEMC");}
|
}
|
}
|
|
|
void on_BtnSendDataScTx_clicked()
|
void on_BtnSendDataScTx_clicked()
|
{
|
{
|
start_send_data = !start_send_data;
|
start_send_data = !start_send_data;
|
if(start_send_data)
|
if(start_send_data)
|
{lblStatus->set_text("SEND DATA ENABLED TX SYSTEMC");}
|
{lblStatus->set_text("SEND DATA ENABLED TX SYSTEMC");}
|
else
|
else
|
{lblStatus->set_text("SEND DATA DISABLED TX SYSTEMC");}
|
{lblStatus->set_text("SEND DATA DISABLED TX SYSTEMC");}
|
}
|
}
|
|
|
void on_BtnGenerateDataSc_clicked()
|
void on_BtnGenerateDataSc_clicked()
|
{
|
{
|
data_generated_sc.clear();
|
data_generated_sc.clear();
|
data_iteration_sc_aux=0;
|
data_iteration_sc_aux=0;
|
data_iteration_sc=0;
|
data_iteration_sc=0;
|
if(CheckBtnEopGenSystemC->get_active())
|
if(CheckBtnEopGenSystemC->get_active())
|
{
|
{
|
for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
|
for(int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
|
{
|
|
if(cnt_max_data == 0 || cnt_max_data == max_data)
|
|
{
|
{
|
intermediate_sc(8,8) = 1;
|
if(cnt_max_data > 0 && cnt_max_data < max_data)
|
intermediate_sc(7,0) = 0;
|
|
}else if(cnt_max_data > 0 && cnt_max_data < max_data)
|
|
{
|
{
|
intermediate_sc(7,0) = data_in(rd);
|
intermediate_sc(7,0) = data_in(rd);
|
intermediate_sc(8,8) = 0;
|
intermediate_sc(8,8) = 0;
|
}
|
}
|
data_generated_sc.push_back(intermediate_sc);
|
data_generated_sc.push_back(intermediate_sc);
|
}
|
}
|
|
|
|
intermediate_sc(8,8) = 1;
|
|
intermediate_sc(7,0) = 0;
|
|
|
|
data_generated_sc.push_back(intermediate_verilog);
|
|
intermediate_sc=0;
|
|
|
}else if(CheckBtnEepGenSystemC->get_active())
|
}else if(CheckBtnEepGenSystemC->get_active())
|
{
|
{
|
for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
|
for(unsigned int cnt_max_data = 0; cnt_max_data <= max_data;cnt_max_data++)
|
{
|
{
|
if(cnt_max_data == 0 || cnt_max_data == max_data)
|
if(cnt_max_data == 0 || cnt_max_data == max_data)
|
{
|
{
|
intermediate_sc(8,8) = 1;
|
intermediate_sc(8,8) = 1;
|
intermediate_sc(7,0) = 1;
|
intermediate_sc(7,0) = 1;
|
}else if(cnt_max_data > 0 && cnt_max_data < max_data)
|
}else if(cnt_max_data > 0 && cnt_max_data < max_data)
|
{
|
{
|
intermediate_sc(7,0) = data_in(rd);
|
intermediate_sc(7,0) = data_in(rd);
|
intermediate_sc(8,8) = 0;
|
intermediate_sc(8,8) = 0;
|
}
|
}
|
data_generated_sc.push_back(intermediate_sc);
|
data_generated_sc.push_back(intermediate_sc);
|
}
|
}
|
intermediate_sc(7,0) = 1;
|
intermediate_sc(7,0) = 1;
|
intermediate_sc(8,8) = 1;
|
intermediate_sc(8,8) = 1;
|
data_generated_sc[nchar(rd)] = intermediate_sc;
|
data_generated_sc[nchar(rd)] = intermediate_sc;
|
}
|
}
|
}
|
}
|
|
|
|
|
void on_BtnChangeFrequencyVerilog_clicked()
|
void on_BtnChangeFrequencyVerilog_clicked()
|
{
|
{
|
string aux = EntryFrequencyVerilog->get_text();
|
string aux = EntryFrequencyVerilog->get_text();
|
|
|
switch(atoi(aux.c_str()))
|
switch(atoi(aux.c_str()))
|
{
|
{
|
case 2:
|
case 2:
|
frquency_nano_second = 500;
|
frquency_nano_second = 500;
|
break;
|
break;
|
case 10:
|
case 10:
|
frquency_nano_second = 100;
|
frquency_nano_second = 100;
|
break;
|
break;
|
case 20:
|
case 20:
|
frquency_nano_second = 50;
|
frquency_nano_second = 50;
|
break;
|
break;
|
case 50:
|
case 50:
|
frquency_nano_second = 20;
|
frquency_nano_second = 20;
|
break;
|
break;
|
case 100:
|
case 100:
|
frquency_nano_second = 10;
|
frquency_nano_second = 10;
|
break;
|
break;
|
case 150:
|
case 150:
|
frquency_nano_second = 7;
|
frquency_nano_second = 7;
|
break;
|
break;
|
case 200:
|
case 200:
|
frquency_nano_second = 5;
|
frquency_nano_second = 5;
|
break;
|
break;
|
case 201:
|
case 201:
|
frquency_nano_second = 4;
|
frquency_nano_second = 4;
|
break;
|
break;
|
case 250:
|
case 250:
|
frquency_nano_second = 4;
|
frquency_nano_second = 4;
|
break;
|
break;
|
case 280:
|
case 280:
|
frquency_nano_second = 3;
|
frquency_nano_second = 3;
|
break;
|
break;
|
default:
|
default:
|
frquency_nano_second = 500;
|
frquency_nano_second = 500;
|
break;
|
break;
|
}
|
}
|
|
|
}
|
}
|
|
|
void thread_gtkmm_run()
|
void thread_gtkmm_run()
|
{
|
{
|
//GRAPHICAL INTERFACE
|
//GRAPHICAL INTERFACE
|
Main Application(true);
|
Main Application(true);
|
builder = Gtk::Builder::create_from_file("SpaceWrireTestSuit.glade");
|
builder = Gtk::Builder::create_from_file("SpaceWrireTestSuit.glade");
|
|
|
builder->get_widget("SpaceWireTestStress", window);
|
builder->get_widget("SpaceWireTestStress", window);
|
builder->get_widget("BtnFinsihSimulation", BtnFinsihSimulation);
|
builder->get_widget("BtnFinsihSimulation", BtnFinsihSimulation);
|
builder->get_widget("BtnLinkEnable", BtnLinkEnable);
|
builder->get_widget("BtnLinkEnable", BtnLinkEnable);
|
builder->get_widget("BtnLinkDisable", BtnLinkDisable);
|
builder->get_widget("BtnLinkDisable", BtnLinkDisable);
|
builder->get_widget("BtnAutoStart", BtnAutoStart);
|
builder->get_widget("BtnAutoStart", BtnAutoStart);
|
builder->get_widget("BtnReset", BtnReset);
|
builder->get_widget("BtnReset", BtnReset);
|
|
|
builder->get_widget("BtnSpaceWireVerilog", BtnSpaceWireVerilog);
|
builder->get_widget("BtnSpaceWireVerilog", BtnSpaceWireVerilog);
|
builder->get_widget("CheckbtnLinkDisable", CheckbtnLinkDisable);
|
builder->get_widget("CheckbtnLinkDisable", CheckbtnLinkDisable);
|
builder->get_widget("CheckbtnAutoStart", CheckbtnAutoStart);
|
builder->get_widget("CheckbtnAutoStart", CheckbtnAutoStart);
|
builder->get_widget("CheckbtnLinkEnable", CheckbtnLinkEnable);
|
builder->get_widget("CheckbtnLinkEnable", CheckbtnLinkEnable);
|
|
|
builder->get_widget("BtnGenerationDataVerilog", BtnGenerationDataVerilog);
|
builder->get_widget("BtnGenerationDataVerilog", BtnGenerationDataVerilog);
|
builder->get_widget("BtnSimpleTest", BtnSimpleTest);
|
builder->get_widget("BtnSimpleTest", BtnSimpleTest);
|
builder->get_widget("CheckBtnEopGenVerilog", CheckBtnEopGenVerilog);
|
builder->get_widget("CheckBtnEopGenVerilog", CheckBtnEopGenVerilog);
|
builder->get_widget("CheckBtnEepGenVerilog", CheckBtnEepGenVerilog);
|
builder->get_widget("CheckBtnEepGenVerilog", CheckBtnEepGenVerilog);
|
builder->get_widget("CheckBtnTimeCodeGenVerilog", CheckBtnTimeCodeGenVerilog);
|
builder->get_widget("CheckBtnTimeCodeGenVerilog", CheckBtnTimeCodeGenVerilog);
|
|
|
builder->get_widget("BtnChangeFrequencyVerilog", BtnChangeFrequencyVerilog);
|
builder->get_widget("BtnChangeFrequencyVerilog", BtnChangeFrequencyVerilog);
|
builder->get_widget("EntryFrequencyVerilog", EntryFrequencyVerilog);
|
builder->get_widget("EntryFrequencyVerilog", EntryFrequencyVerilog);
|
|
|
builder->get_widget("BtnTxFrequency", BtnTxFrequency);
|
builder->get_widget("BtnTxFrequency", BtnTxFrequency);
|
builder->get_widget("EntryFrequency", EntryFrequency);
|
builder->get_widget("EntryFrequency", EntryFrequency);
|
|
|
builder->get_widget("BtnSendDataScTx", BtnSendDataScTx);
|
builder->get_widget("BtnSendDataScTx", BtnSendDataScTx);
|
builder->get_widget("BtnTimeCodeScTx", BtnTimeCodeScTx);
|
builder->get_widget("BtnTimeCodeScTx", BtnTimeCodeScTx);
|
builder->get_widget("BtnGenerateDataSc", BtnGenerateDataSc);
|
builder->get_widget("BtnGenerateDataSc", BtnGenerateDataSc);
|
builder->get_widget("CheckBtnEepGenSystemC", CheckBtnEepGenSystemC);
|
builder->get_widget("CheckBtnEepGenSystemC", CheckBtnEepGenSystemC);
|
builder->get_widget("CheckBtnEopGenSystemC", CheckBtnEopGenSystemC);
|
builder->get_widget("CheckBtnEopGenSystemC", CheckBtnEopGenSystemC);
|
|
|
builder->get_widget("lblStatus",lblStatus);
|
builder->get_widget("lblStatus",lblStatus);
|
|
|
BtnFinsihSimulation->signal_clicked().connect(sigc::ptr_fun(&on_BtnFinsihSimulation_clicked));
|
BtnFinsihSimulation->signal_clicked().connect(sigc::ptr_fun(&on_BtnFinsihSimulation_clicked));
|
BtnLinkEnable->signal_clicked().connect(sigc::ptr_fun(&on_BtnLinkEnable_clicked));
|
BtnLinkEnable->signal_clicked().connect(sigc::ptr_fun(&on_BtnLinkEnable_clicked));
|
BtnLinkDisable->signal_clicked().connect(sigc::ptr_fun(&on_BtnLinkDisable_clicked));
|
BtnLinkDisable->signal_clicked().connect(sigc::ptr_fun(&on_BtnLinkDisable_clicked));
|
BtnAutoStart->signal_clicked().connect(sigc::ptr_fun(&on_BtnAutoStart_clicked));
|
BtnAutoStart->signal_clicked().connect(sigc::ptr_fun(&on_BtnAutoStart_clicked));
|
BtnReset->signal_clicked().connect(sigc::ptr_fun(&on_BtnReset_clicked));
|
BtnReset->signal_clicked().connect(sigc::ptr_fun(&on_BtnReset_clicked));
|
|
|
BtnSpaceWireVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnSpaceWireVerilog_clicked));
|
BtnSpaceWireVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnSpaceWireVerilog_clicked));
|
|
|
BtnSimpleTest->signal_clicked().connect(sigc::ptr_fun(&on_BtnSimpleTest_clicked));
|
BtnSimpleTest->signal_clicked().connect(sigc::ptr_fun(&on_BtnSimpleTest_clicked));
|
|
|
BtnChangeFrequencyVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnChangeFrequencyVerilog_clicked));
|
BtnChangeFrequencyVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnChangeFrequencyVerilog_clicked));
|
|
|
BtnGenerationDataVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnGenerationDataVerilog_clicked));
|
BtnGenerationDataVerilog->signal_clicked().connect(sigc::ptr_fun(&on_BtnGenerationDataVerilog_clicked));
|
|
|
BtnTxFrequency->signal_clicked().connect(sigc::ptr_fun(&on_BtnTxFrequency_clicked));
|
BtnTxFrequency->signal_clicked().connect(sigc::ptr_fun(&on_BtnTxFrequency_clicked));
|
|
|
BtnSendDataScTx->signal_clicked().connect(sigc::ptr_fun(&on_BtnSendDataScTx_clicked));
|
BtnSendDataScTx->signal_clicked().connect(sigc::ptr_fun(&on_BtnSendDataScTx_clicked));
|
BtnTimeCodeScTx->signal_clicked().connect(sigc::ptr_fun(&on_BtnTimeCodeScTx_clicked));
|
BtnTimeCodeScTx->signal_clicked().connect(sigc::ptr_fun(&on_BtnTimeCodeScTx_clicked));
|
BtnGenerateDataSc->signal_clicked().connect(sigc::ptr_fun(&on_BtnGenerateDataSc_clicked));
|
BtnGenerateDataSc->signal_clicked().connect(sigc::ptr_fun(&on_BtnGenerateDataSc_clicked));
|
|
|
window->set_title("GLADIC SPACEWIRE TEST TOOL");
|
window->set_title("GLADIC SPACEWIRE TEST TOOL");
|
|
|
Application.run(*window);
|
Application.run(*window);
|
}
|
}
|
|
|
Control_SC::Control_SC()
|
Control_SC::Control_SC()
|
{
|
{
|
clock_systemc = 2;
|
clock_systemc = 2;
|
sn_top = new sc_TOP_SPW("sc_TOP_SPW");
|
sn_top = new sc_TOP_SPW("sc_TOP_SPW");
|
boost::thread workerThreadGTKMM(thread_gtkmm_run);
|
boost::thread workerThreadGTKMM(thread_gtkmm_run);
|
|
|
data_col_store.push_back("CONTROL TYPE");
|
data_col_store.push_back("CONTROL TYPE");
|
data_col_store.push_back("NUMBER GENERATED");
|
data_col_store.push_back("NUMBER GENERATED");
|
data_col_store.push_back("NUMBER RECEIVED");
|
data_col_store.push_back("NUMBER RECEIVED");
|
data_col_store.push_back("COMPARE");
|
data_col_store.push_back("COMPARE");
|
data_col_store.push_back("TIME STAMP");
|
data_col_store.push_back("TIME STAMP");
|
REC_TX_SPW = new data_recorder("test_suit_vlog_sc.html",data_col_store,"test_suit_vlog_sc.html","TX VERILOG 2 RX SYSTEMC");
|
REC_TX_SPW = new data_recorder("test_suit_vlog_sc.html",data_col_store,"test_suit_vlog_sc.html","TX VERILOG 2 RX SYSTEMC");
|
REC_TX_SPW->initialize();
|
REC_TX_SPW->initialize();
|
COMPARE_SPW = new data_check();
|
COMPARE_SPW = new data_check();
|
data_col_store.clear();
|
data_col_store.clear();
|
|
|
data_col_store0.push_back("CONTROL TYPE");
|
data_col_store0.push_back("CONTROL TYPE");
|
data_col_store0.push_back("NUMBER GENERATED");
|
data_col_store0.push_back("NUMBER GENERATED");
|
data_col_store0.push_back("NUMBER RECEIVED");
|
data_col_store0.push_back("NUMBER RECEIVED");
|
data_col_store0.push_back("COMPARE");
|
data_col_store0.push_back("COMPARE");
|
data_col_store0.push_back("TIME STAMP");
|
data_col_store0.push_back("TIME STAMP");
|
REC_TX_SPWSC = new data_recorder("test_suit_sc_vlog.html",data_col_store0,"test_suit_sc_vlog.html","TX SYSTEMC 2 RX VERILOG");
|
REC_TX_SPWSC = new data_recorder("test_suit_sc_vlog.html",data_col_store0,"test_suit_sc_vlog.html","TX SYSTEMC 2 RX VERILOG");
|
COMPARE_SPW_RX = new data_check();
|
COMPARE_SPW_RX = new data_check();
|
REC_TX_SPWSC->initialize();
|
REC_TX_SPWSC->initialize();
|
data_col_store0.clear();
|
data_col_store0.clear();
|
}
|
}
|
|
|
void Control_SC::init()
|
void Control_SC::init()
|
{
|
{
|
|
|
sn_top->RESET = true;
|
sn_top->RESET = true;
|
|
|
sn_top->LINK_DISABLE = false;
|
sn_top->LINK_DISABLE = false;
|
sn_top->LINK_START = false;
|
sn_top->LINK_START = false;
|
sn_top->AUTO_START = false;
|
sn_top->AUTO_START = false;
|
|
|
sn_top->E_SEND_DATA = false;
|
sn_top->E_SEND_DATA = false;
|
|
|
sn_top->CLOCK_GEN = 1;
|
sn_top->CLOCK_GEN = 1;
|
frquency_nano_second = 500;
|
frquency_nano_second = 500;
|
//sn_top->TICKIN_TX = false;
|
|
//sn_top->TIMEIN_CONTROL_FLAG_TX = 0;
|
|
|
|
//sn_top->TXWRITE_TX = false;
|
|
//sn_top->TXDATA_FLAGCTRL_TX = 0;
|
|
}
|
}
|
|
|
void autostart()
|
void autostart()
|
{
|
{
|
if(auto_start)
|
if(auto_start)
|
{
|
{
|
sn_top->AUTO_START = true;
|
sn_top->AUTO_START = true;
|
//lblStatus->set_text("AUTOSTART ENABLED ON TX SYSTEMC");
|
//lblStatus->set_text("AUTOSTART ENABLED ON TX SYSTEMC");
|
}
|
}
|
else
|
else
|
{
|
{
|
sn_top->AUTO_START = false;
|
sn_top->AUTO_START = false;
|
//lblStatus->set_text("AUTOSTART DISABLED ON TX SYSTEMC");
|
//lblStatus->set_text("AUTOSTART DISABLED ON TX SYSTEMC");
|
}
|
}
|
}
|
}
|
|
|
void linkstart()
|
void linkstart()
|
{
|
{
|
if(link_start)
|
if(link_start)
|
{
|
{
|
sn_top->LINK_START = true;
|
sn_top->LINK_START = true;
|
//lblStatus->set_text("LINKSTART ENABLED ON TX SYSTEMC");
|
//lblStatus->set_text("LINKSTART ENABLED ON TX SYSTEMC");
|
}
|
}
|
else
|
else
|
{
|
{
|
sn_top->LINK_START = false;
|
sn_top->LINK_START = false;
|
//lblStatus->set_text("LINKSTART DISABLED ON TX SYSTEMC");
|
//lblStatus->set_text("LINKSTART DISABLED ON TX SYSTEMC");
|
}
|
}
|
}
|
}
|
|
|
void linkdisable()
|
void linkdisable()
|
{
|
{
|
if(link_disable)
|
if(link_disable)
|
{
|
{
|
sn_top->LINK_DISABLE = true;
|
sn_top->LINK_DISABLE = true;
|
//lblStatus->set_text("LINKDISABLE ENABLED ON TX SYSTEMC");
|
//lblStatus->set_text("LINKDISABLE ENABLED ON TX SYSTEMC");
|
}
|
}
|
else
|
else
|
{
|
{
|
sn_top->LINK_DISABLE = false;
|
sn_top->LINK_DISABLE = false;
|
//lblStatus->set_text("LINKDISABLE DISABLED ON TX SYSTEMC");
|
//lblStatus->set_text("LINKDISABLE DISABLED ON TX SYSTEMC");
|
}
|
}
|
}
|
}
|
|
|
void send_data_tx_sc()
|
void send_data_tx_sc()
|
{
|
{
|
if(start_send_data)
|
if(start_send_data)
|
{
|
{
|
sn_top->E_SEND_DATA = true;
|
sn_top->E_SEND_DATA = true;
|
}
|
}
|
else
|
else
|
{
|
{
|
sn_top->E_SEND_DATA = false;
|
sn_top->E_SEND_DATA = false;
|
}
|
}
|
|
|
}
|
}
|
|
|
void Control_SC::run_sim()
|
void Control_SC::run_sim()
|
{
|
{
|
|
|
autostart();
|
autostart();
|
linkstart();
|
linkstart();
|
linkdisable();
|
linkdisable();
|
send_data_tx_sc();
|
send_data_tx_sc();
|
|
|
sc_start(clock_systemc,SC_NS);
|
sc_start(clock_systemc,SC_NS);
|
|
|
}
|
}
|
|
|
/* END OF SIMULATION */
|
/* END OF SIMULATION */
|
void Control_SC::stop_sim()
|
void Control_SC::stop_sim()
|
{
|
{
|
sc_stop();
|
sc_stop();
|
}
|
}
|
|
|
/* RESET HIGH */
|
/* RESET HIGH */
|
bool Control_SC::reset_set()
|
bool Control_SC::reset_set()
|
{
|
{
|
|
|
if(global_reset)
|
if(global_reset)
|
{
|
{
|
sn_top->RESET = false;
|
sn_top->RESET = false;
|
}else
|
}else
|
{
|
{
|
sn_top->RESET = true;
|
sn_top->RESET = true;
|
}
|
}
|
|
|
return sn_top->RESET;
|
return sn_top->RESET;
|
}
|
}
|
|
|
unsigned int Control_SC::get_value_dout()
|
unsigned int Control_SC::get_value_dout()
|
{
|
{
|
return sn_top->DOUT.read();
|
return sn_top->DOUT.read();
|
}
|
}
|
|
|
unsigned int Control_SC::get_value_sout()
|
unsigned int Control_SC::get_value_sout()
|
{
|
{
|
return sn_top->SOUT.read();
|
return sn_top->SOUT.read();
|
}
|
}
|
|
|
void Control_SC::set_rx_sin(unsigned int strobe)
|
void Control_SC::set_rx_sin(unsigned int strobe)
|
{
|
{
|
sn_top->SIN = strobe;
|
sn_top->SIN = strobe;
|
}
|
}
|
|
|
void Control_SC::set_rx_din(unsigned int data)
|
void Control_SC::set_rx_din(unsigned int data)
|
{
|
{
|
sn_top->DIN = data;
|
sn_top->DIN = data;
|
}
|
}
|
|
|
unsigned int Control_SC::get_spw_fsm()
|
unsigned int Control_SC::get_spw_fsm()
|
{
|
{
|
return sn_top->FSM_SPW_OUT.read();
|
return sn_top->FSM_SPW_OUT.read();
|
}
|
}
|
|
|
unsigned int Control_SC::finish_simulation()
|
unsigned int Control_SC::finish_simulation()
|
{
|
{
|
return finish;
|
return finish;
|
}
|
}
|
|
|
//verilog variables
|
//verilog variables
|
bool Control_SC::verilog_linkenable()
|
bool Control_SC::verilog_linkenable()
|
{
|
{
|
return verilog_link_start;
|
return verilog_link_start;
|
}
|
}
|
|
|
bool Control_SC::verilog_autostart()
|
bool Control_SC::verilog_autostart()
|
{
|
{
|
return verilog_auto_start;
|
return verilog_auto_start;
|
}
|
}
|
|
|
bool Control_SC::verilog_linkdisable()
|
bool Control_SC::verilog_linkdisable()
|
{
|
{
|
return verilog_link_disable;
|
return verilog_link_disable;
|
}
|
}
|
|
|
float Control_SC::verilog_frequency()
|
float Control_SC::verilog_frequency()
|
{
|
{
|
return frquency_nano_second;
|
return frquency_nano_second;
|
}
|
}
|
|
|
//Test verilog
|
//Test verilog
|
bool Control_SC::start_tx_test()
|
bool Control_SC::start_tx_test()
|
{
|
{
|
return start_send_data_verilog;
|
return start_send_data_verilog;
|
}
|
}
|
|
|
bool Control_SC::enable_time_code_tx_test()
|
bool Control_SC::enable_time_code_tx_test()
|
{
|
{
|
return enable_time_code_verilog;
|
return enable_time_code_verilog;
|
}
|
}
|
|
|
void Control_SC::end_tx_test()
|
void Control_SC::end_tx_test()
|
{
|
{
|
start_send_data_verilog = enable_time_code_verilog = false;
|
start_send_data_verilog = enable_time_code_verilog = false;
|
}
|
}
|
|
|
int Control_SC::size_data_test()
|
int Control_SC::size_data_test_vlog()
|
|
{
|
|
return data_generated_verilog.size();
|
|
}
|
|
|
|
int Control_SC::size_data_test_sc()
|
{
|
{
|
return data_generated_verilog.size()-1;
|
return data_generated_sc.size();
|
}
|
}
|
|
|
unsigned int Control_SC::take_data(unsigned int a)
|
unsigned int Control_SC::take_data(unsigned int a)
|
{
|
{
|
intermediate = data_generated_verilog[a];
|
intermediate = data_generated_verilog[a];
|
return intermediate(8,0);
|
return intermediate(8,0);
|
}
|
}
|
|
|
void Control_SC::data_o(unsigned int data, unsigned int pos)
|
void Control_SC::data_o(unsigned int data, unsigned int pos)
|
{
|
{
|
sc_uint<9> intermediate = data;
|
sc_uint<9> intermediate = data;
|
|
|
data_col_store0.clear();
|
data_col_store0.clear();
|
if(data_iteration_sc <= data_generated_sc.size()-1)
|
if(data_iteration_sc <= data_generated_sc.size()-1)
|
{
|
{
|
data_col_store0.push_back("DATA");
|
data_col_store0.push_back("DATA");
|
|
|
intermediate_sc=data_generated_sc[pos];
|
intermediate_sc=data_generated_sc[pos];
|
data_col_store0.push_back(intermediate_sc.to_string(SC_HEX));
|
data_col_store0.push_back(intermediate_sc.to_string(SC_HEX));
|
|
|
data_col_store0.push_back(intermediate.to_string(SC_HEX));
|
data_col_store0.push_back(intermediate.to_string(SC_HEX));
|
|
|
data_col_store0.push_back(" ");
|
data_col_store0.push_back(" ");
|
COMPARE_SPW_RX->compare_test(&data_col_store0);
|
COMPARE_SPW_RX->compare_test(&data_col_store0);
|
|
|
data_col_store0.push_back(sc_time_stamp().to_string());
|
data_col_store0.push_back(sc_time_stamp().to_string());
|
REC_TX_SPWSC->storedata(data_col_store0);
|
REC_TX_SPWSC->storedata(data_col_store0);
|
data_iteration_sc++;
|
data_iteration_sc++;
|
}else
|
}else
|
{
|
{
|
data_iteration_sc = 0;
|
data_iteration_sc = 0;
|
}
|
}
|
}
|
}
|
|
|
|
|
|
void Control_SC::data_rx_vlog_loopback_o(unsigned int data, unsigned int pos)
|
|
{
|
|
|
|
sc_uint<9> intermediate;
|
|
|
|
data_col_store.clear();
|
|
|
|
data_col_store.push_back("DATA");
|
|
intermediate = data_generated_verilog[pos];
|
|
data_col_store.push_back(intermediate.to_string(SC_HEX));
|
|
|
|
intermediate = data;
|
|
data_col_store.push_back(intermediate(8,0).to_string(SC_HEX));
|
|
data_col_store.push_back(" ");
|
|
COMPARE_SPW->compare_test(&data_col_store);
|
|
|
|
data_col_store.push_back(sc_time_stamp().to_string());
|
|
REC_TX_SPW->storedata(data_col_store);
|
|
}
|
|
|
|
void data_rx_sc_o(unsigned int type_char, sc_uint<4> control, sc_uint<4> last_control_sys , sc_uint<10> data , sc_uint<10> timecode_sys)
|
|
{
|
|
data_col_store.clear();
|
|
|
|
switch(type_char)
|
|
{
|
|
case 0:
|
|
data_col_store.push_back("NULL");
|
|
data_col_store.push_back(" - ");
|
|
data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
|
|
data_col_store.push_back(" - ");
|
|
data_col_store.push_back(sc_time_stamp().to_string());
|
|
REC_TX_SPW->storedata(data_col_store);
|
|
break;
|
|
case 1:
|
|
data_col_store.push_back("FCT");
|
|
data_col_store.push_back(" - ");
|
|
data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
|
|
data_col_store.push_back(" - ");
|
|
data_col_store.push_back(sc_time_stamp().to_string());
|
|
REC_TX_SPW->storedata(data_col_store);
|
|
break;
|
|
case 2:
|
|
data_col_store.push_back("EOP");
|
|
intermediate_data = data_generated_verilog[data_iteration];
|
|
data_col_store.push_back(intermediate_data.to_string(SC_HEX));
|
|
data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
|
|
data_col_store.push_back(" ");
|
|
COMPARE_SPW->compare_test(&data_col_store);
|
|
data_iteration++;
|
|
data_col_store.push_back(sc_time_stamp().to_string());
|
|
REC_TX_SPW->storedata(data_col_store);
|
|
break;
|
|
case 3:
|
|
data_col_store.push_back("EEP");
|
|
intermediate_data = data_generated_verilog[data_iteration];
|
|
data_col_store.push_back(intermediate_data.to_string(SC_HEX));
|
|
|
|
data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
|
|
data_col_store.push_back(" ");
|
|
COMPARE_SPW->compare_test(&data_col_store);
|
|
data_iteration++;
|
|
|
|
data_col_store.push_back(sc_time_stamp().to_string());
|
|
REC_TX_SPW->storedata(data_col_store);
|
|
break;
|
|
case 4:
|
|
data_col_store.push_back("INVALID CONNECTION");
|
|
data_col_store.push_back(" - ");
|
|
data_col_store.push_back(last_control_sys(2,0).to_string(SC_HEX) + control(2,0).to_string());
|
|
data_col_store.push_back(" - ");
|
|
data_col_store.push_back(sc_time_stamp().to_string());
|
|
REC_TX_SPW->storedata(data_col_store);
|
|
break;
|
|
case 5:
|
|
data_col_store.push_back("DATA");
|
|
intermediate_data = data_generated_verilog[data_iteration];
|
|
data_col_store.push_back(intermediate_data.to_string(SC_HEX));
|
|
|
|
data_col_store.push_back(data(8,0).to_string(SC_HEX));
|
|
data_col_store.push_back(" ");
|
|
COMPARE_SPW->compare_test(&data_col_store);
|
|
|
|
data_col_store.push_back(sc_time_stamp().to_string());
|
|
REC_TX_SPW->storedata(data_col_store);
|
|
data_iteration++;
|
|
break;
|
|
case 6:
|
|
data_col_store.push_back("TIMECODE");
|
|
data_col_store.push_back(" - ");
|
|
data_col_store.push_back(timecode_sys(7,0).to_string());
|
|
data_col_store.push_back(" - ");
|
|
data_col_store.push_back(sc_time_stamp().to_string());
|
|
REC_TX_SPW->storedata(data_col_store);
|
|
break;
|
|
}
|
|
|
|
}
|
|
|
unsigned int Control_SC::clock_tx()
|
unsigned int Control_SC::clock_tx()
|
{
|
{
|
return sn_top->DUT.CLOCK_TX_OUT.read();
|
return sn_top->DUT.CLOCK_TX_OUT.read();
|
}
|
}
|
|
|
|
|
