-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--*
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--*
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--* @short OPB-Slave Interface
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--* @short OPB-Slave Interface
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--*
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--*
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--* Generics described in top entity.
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--* Generics described in top entity.
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--*
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--*
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--* @see opb_spi_slave
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--* @see opb_spi_slave
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--* @author: Daniel Köthe
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--* @author: Daniel Köthe
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--* @version: 1.0
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--* @version: 1.0
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--* @date: 2007-11-11
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--* @date: 2007-11-11
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--/
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--/
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.numeric_std.all; -- conv_integer()
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use IEEE.numeric_std.all; -- conv_integer()
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|
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library work;
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library work;
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use work.opb_spi_slave_pack.all;
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use work.opb_spi_slave_pack.all;
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|
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entity opb_if is
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entity opb_if is
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generic (
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generic (
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C_BASEADDR : std_logic_vector(0 to 31) := X"00000000";
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C_BASEADDR : std_logic_vector(0 to 31) := X"00000000";
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C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
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C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
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C_USER_ID_CODE : integer := 3;
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C_USER_ID_CODE : integer := 3;
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C_OPB_AWIDTH : integer := 32;
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C_OPB_AWIDTH : integer := 32;
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C_OPB_DWIDTH : integer := 32;
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C_OPB_DWIDTH : integer := 32;
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C_FAMILY : string := "virtex-4";
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C_FAMILY : string := "virtex-4";
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C_SR_WIDTH : integer := 8;
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C_SR_WIDTH : integer := 8;
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C_FIFO_SIZE_WIDTH : integer := 4;
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C_FIFO_SIZE_WIDTH : integer := 4;
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C_DMA_EN : boolean := false;
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C_DMA_EN : boolean := false;
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C_CRC_EN : boolean := false);
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C_CRC_EN : boolean := false);
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port (
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port (
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-- OPB-Bus Signals
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-- OPB-Bus Signals
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OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
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OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
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OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
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OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
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OPB_Clk : in std_logic;
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OPB_Clk : in std_logic;
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OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
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OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
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OPB_RNW : in std_logic;
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OPB_RNW : in std_logic;
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OPB_Rst : in std_logic;
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OPB_Rst : in std_logic;
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OPB_select : in std_logic;
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OPB_select : in std_logic;
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OPB_seqAddr : in std_logic;
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OPB_seqAddr : in std_logic;
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Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
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Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
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Sln_errAck : out std_logic;
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Sln_errAck : out std_logic;
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Sln_retry : out std_logic;
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Sln_retry : out std_logic;
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Sln_toutSup : out std_logic;
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Sln_toutSup : out std_logic;
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Sln_xferAck : out std_logic;
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Sln_xferAck : out std_logic;
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-- fifo ports
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-- fifo ports
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opb_s_tx_en : out std_logic;
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opb_s_tx_en : out std_logic;
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opb_s_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0);
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opb_s_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0);
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opb_s_rx_en : out std_logic;
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opb_s_rx_en : out std_logic;
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opb_s_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0);
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opb_s_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0);
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-- control register
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-- control register
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opb_ctl_reg : out std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0);
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opb_ctl_reg : out std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0);
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-- Fifo almost full/empty thresholds
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-- Fifo almost full/empty thresholds
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tx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);
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tx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);
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rx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);
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rx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);
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opb_fifo_flg : in std_logic_vector(C_NUM_FLG-1 downto 0);
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opb_fifo_flg : in std_logic_vector(C_NUM_FLG-1 downto 0);
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-- interrupts
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-- interrupts
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opb_dgie : out std_logic;
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opb_dgie : out std_logic;
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opb_ier : out std_logic_vector(C_NUM_INT-1 downto 0);
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opb_ier : out std_logic_vector(C_NUM_INT-1 downto 0);
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opb_isr : in std_logic_vector(C_NUM_INT-1 downto 0);
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opb_isr : in std_logic_vector(C_NUM_INT-1 downto 0);
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opb_isr_clr : out std_logic_vector(C_NUM_INT-1 downto 0);
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opb_isr_clr : out std_logic_vector(C_NUM_INT-1 downto 0);
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-- dma register
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-- dma register
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opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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opb_tx_dma_ctl : out std_logic_vector(0 downto 0);
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opb_tx_dma_ctl : out std_logic_vector(0 downto 0);
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opb_tx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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opb_tx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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opb_rx_dma_ctl : out std_logic_vector(0 downto 0);
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opb_rx_dma_ctl : out std_logic_vector(0 downto 0);
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opb_rx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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opb_rx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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-- rx crc
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-- rx crc
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opb_rx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0);
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opb_rx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0);
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opb_tx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0));
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opb_tx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0));
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end opb_if;
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end opb_if;
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architecture behavior of opb_if is
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architecture behavior of opb_if is
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signal Sln_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal Sln_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal OPB_ABus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal OPB_ABus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal OPB_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal OPB_DBus_big_end : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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type state_t is (idle,
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type state_t is (idle,
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done);
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done);
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signal state : state_t := idle;
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signal state : state_t := idle;
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-- internal signals to enable readback
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-- internal signals to enable readback
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signal tx_thresh_int : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);
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signal tx_thresh_int : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);
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signal rx_thresh_int : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);
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signal rx_thresh_int : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);
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signal opb_ier_int : std_logic_vector(C_NUM_INT-1 downto 0);
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signal opb_ier_int : std_logic_vector(C_NUM_INT-1 downto 0);
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signal opb_dgie_int : std_logic;
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signal opb_dgie_int : std_logic;
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signal opb_ctl_reg_int : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0);
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signal opb_ctl_reg_int : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0);
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-- only used if C_DMA_EN=true
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-- only used if C_DMA_EN=true
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signal opb_tx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal opb_tx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal opb_tx_dma_ctl_int : std_logic_vector(0 downto 0);
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signal opb_tx_dma_ctl_int : std_logic_vector(0 downto 0);
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signal opb_tx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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signal opb_tx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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signal opb_rx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal opb_rx_dma_addr_int : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
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signal opb_rx_dma_ctl_int : std_logic_vector(0 downto 0);
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signal opb_rx_dma_ctl_int : std_logic_vector(0 downto 0);
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signal opb_rx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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signal opb_rx_dma_num_int : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
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begin -- behavior
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begin -- behavior
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tx_thresh <= tx_thresh_int;
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tx_thresh <= tx_thresh_int;
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rx_thresh <= rx_thresh_int;
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rx_thresh <= rx_thresh_int;
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opb_ier <= opb_ier_int;
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opb_ier <= opb_ier_int;
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opb_dgie <= opb_dgie_int;
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opb_dgie <= opb_dgie_int;
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opb_ctl_reg <= opb_ctl_reg_int;
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opb_ctl_reg <= opb_ctl_reg_int;
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--* Signals for DMA-Engine control
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--* Signals for DMA-Engine control
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u1 : if C_DMA_EN generate
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u1 : if C_DMA_EN generate
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opb_tx_dma_ctl <= opb_tx_dma_ctl_int;
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opb_tx_dma_ctl <= opb_tx_dma_ctl_int;
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opb_tx_dma_addr <= opb_tx_dma_addr_int;
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opb_tx_dma_addr <= opb_tx_dma_addr_int;
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opb_tx_dma_num <= opb_tx_dma_num_int;
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opb_tx_dma_num <= opb_tx_dma_num_int;
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opb_rx_dma_ctl <= opb_rx_dma_ctl_int;
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opb_rx_dma_ctl <= opb_rx_dma_ctl_int;
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opb_rx_dma_addr <= opb_rx_dma_addr_int;
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opb_rx_dma_addr <= opb_rx_dma_addr_int;
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opb_rx_dma_num <= opb_rx_dma_num_int;
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opb_rx_dma_num <= opb_rx_dma_num_int;
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end generate u1;
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end generate u1;
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-- unused outputs
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-- unused outputs
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Sln_errAck <= '0';
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Sln_errAck <= '0';
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Sln_retry <= '0';
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Sln_retry <= '0';
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Sln_toutSup <= '0';
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Sln_toutSup <= '0';
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--* convert Sln_DBus_big_end to little mode
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--* convert Sln_DBus_big_end to little mode
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conv_big_Sln_DBus_proc : process(Sln_DBus_big_end)
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conv_big_Sln_DBus_proc : process(Sln_DBus_big_end)
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begin
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begin
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for i in 0 to 31 loop
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for i in 0 to 31 loop
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Sln_DBus(31-i) <= Sln_DBus_big_end(i);
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Sln_DBus(31-i) <= Sln_DBus_big_end(i);
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end loop; -- i
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end loop; -- i
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end process conv_big_Sln_DBus_proc;
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end process conv_big_Sln_DBus_proc;
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--* convert OPB_ABus to big endian
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--* convert OPB_ABus to big endian
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conv_big_OPB_ABus_proc : process(OPB_ABus)
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conv_big_OPB_ABus_proc : process(OPB_ABus)
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begin
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begin
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for i in 0 to 31 loop
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for i in 0 to 31 loop
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OPB_ABus_big_end(31-i) <= OPB_ABus(i);
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OPB_ABus_big_end(31-i) <= OPB_ABus(i);
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end loop; -- i
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end loop; -- i
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end process conv_big_OPB_ABus_proc;
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end process conv_big_OPB_ABus_proc;
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--* convert OPB_DBus to little mode
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--* convert OPB_DBus to little mode
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conv_big_OPB_DBus_proc : process(OPB_DBus)
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conv_big_OPB_DBus_proc : process(OPB_DBus)
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begin
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begin
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for i in 0 to 31 loop
|
for i in 0 to 31 loop
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OPB_DBus_big_end(31-i) <= OPB_DBus(i);
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OPB_DBus_big_end(31-i) <= OPB_DBus(i);
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end loop; -- i
|
end loop; -- i
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end process conv_big_OPB_DBus_proc;
|
end process conv_big_OPB_DBus_proc;
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|
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--* control OPB requests
|
--* control OPB requests
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--*
|
--*
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--* handles OPB-read and -write request
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--* handles OPB-read and -write request
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opb_slave_proc : process (OPB_Rst, OPB_Clk)
|
opb_slave_proc : process (OPB_Rst, OPB_Clk)
|
begin
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begin
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if (OPB_Rst = '1') then
|
if (OPB_Rst = '1') then
|
-- OPB
|
-- OPB
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Sln_xferAck <= '0';
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Sln_xferAck <= '0';
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Sln_DBus_big_end <= (others => '0');
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Sln_DBus_big_end <= (others => '0');
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-- FIFO
|
-- FIFO
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opb_s_rx_en <= '0';
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opb_s_rx_en <= '0';
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opb_s_tx_en <= '0';
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opb_s_tx_en <= '0';
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--
|
--
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state <= idle;
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state <= idle;
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-- Register
|
-- Register
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tx_thresh_int <= (others => '0');
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tx_thresh_int <= (others => '0');
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rx_thresh_int <= (others => '0');
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rx_thresh_int <= (others => '0');
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opb_ier_int <= (others => '0');
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opb_ier_int <= (others => '0');
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opb_dgie_int <= '0';
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opb_dgie_int <= '0';
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opb_ctl_reg_int <= (others => '0');
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opb_ctl_reg_int <= (others => '0');
|
|
|
if C_DMA_EN then
|
if C_DMA_EN then
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opb_tx_dma_ctl_int <= (others => '0');
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opb_tx_dma_ctl_int <= (others => '0');
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opb_tx_dma_addr_int <= (others => '0');
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opb_tx_dma_addr_int <= (others => '0');
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opb_tx_dma_num_int <= (others => '0');
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opb_tx_dma_num_int <= (others => '0');
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opb_rx_dma_ctl_int <= (others => '0');
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opb_rx_dma_ctl_int <= (others => '0');
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opb_rx_dma_addr_int <= (others => '0');
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opb_rx_dma_addr_int <= (others => '0');
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opb_rx_dma_num_int <= (others => '0');
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opb_rx_dma_num_int <= (others => '0');
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end if;
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end if;
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elsif (OPB_Clk'event and OPB_Clk = '1') then
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elsif (OPB_Clk'event and OPB_Clk = '1') then
|
case state is
|
case state is
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when idle =>
|
when idle =>
|
if (OPB_select = '1' and
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if (OPB_select = '1' and
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((OPB_ABus >= C_BASEADDR) and (OPB_ABus <= C_HIGHADDR))) then
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((OPB_ABus >= C_BASEADDR) and (OPB_ABus <= C_HIGHADDR))) then
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-- *device selected
|
-- *device selected
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Sln_xferAck <= '1';
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Sln_xferAck <= '1';
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state <= done;
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state <= done;
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if (OPB_RNW = '1') then
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if (OPB_RNW = '1') then
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-- read acess
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-- read acess
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case OPB_ABus_big_end(7 downto 2) is
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case OPB_ABus_big_end(7 downto 2) is
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when C_ADR_CTL =>
|
when C_ADR_CTL =>
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Sln_DBus_big_end(C_OPB_CTL_REG_WIDTH-1 downto 0) <= opb_ctl_reg_int;
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Sln_DBus_big_end(C_OPB_CTL_REG_WIDTH-1 downto 0) <= opb_ctl_reg_int;
|
|
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when C_ADR_RX_DATA =>
|
when C_ADR_RX_DATA =>
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opb_s_rx_en <= '1';
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opb_s_rx_en <= '1';
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Sln_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_s_rx_data;
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Sln_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_s_rx_data;
|
|
|
when C_ADR_STATUS =>
|
when C_ADR_STATUS =>
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Sln_DBus_big_end(C_NUM_FLG-1 downto 0) <= opb_fifo_flg;
|
Sln_DBus_big_end(C_NUM_FLG-1 downto 0) <= opb_fifo_flg;
|
|
|
when C_ADR_TX_THRESH =>
|
when C_ADR_TX_THRESH =>
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Sln_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0) <= tx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0);
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Sln_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0) <= tx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0);
|
Sln_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16) <= tx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH);
|
Sln_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16) <= tx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH);
|
|
|
when C_ADR_RX_THRESH =>
|
when C_ADR_RX_THRESH =>
|
Sln_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0) <= rx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0);
|
Sln_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0) <= rx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0);
|
Sln_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16) <= rx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH);
|
Sln_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16) <= rx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH);
|
|
|
when C_ADR_DGIE =>
|
when C_ADR_DGIE =>
|
Sln_DBus_big_end(0) <= opb_dgie_int;
|
Sln_DBus_big_end(0) <= opb_dgie_int;
|
when C_ADR_IER =>
|
when C_ADR_IER =>
|
Sln_DBus_big_end(C_NUM_INT-1 downto 0) <= opb_ier_int;
|
Sln_DBus_big_end(C_NUM_INT-1 downto 0) <= opb_ier_int;
|
|
|
when C_ADR_ISR =>
|
when C_ADR_ISR =>
|
Sln_DBus_big_end(C_NUM_INT-1 downto 0) <= opb_isr;
|
Sln_DBus_big_end(C_NUM_INT-1 downto 0) <= opb_isr;
|
|
|
when C_ADR_TX_DMA_CTL =>
|
when C_ADR_TX_DMA_CTL =>
|
if C_DMA_EN then
|
if C_DMA_EN then
|
Sln_DBus_big_end(0 downto 0) <= opb_tx_dma_ctl_int;
|
Sln_DBus_big_end(0 downto 0) <= opb_tx_dma_ctl_int;
|
end if;
|
end if;
|
|
|
when C_ADR_TX_DMA_ADDR =>
|
when C_ADR_TX_DMA_ADDR =>
|
if C_DMA_EN then
|
if C_DMA_EN then
|
Sln_DBus_big_end(C_OPB_DWIDTH-1 downto 0) <= opb_tx_dma_addr_int;
|
Sln_DBus_big_end(C_OPB_DWIDTH-1 downto 0) <= opb_tx_dma_addr_int;
|
end if;
|
end if;
|
|
|
when C_ADR_TX_DMA_NUM =>
|
when C_ADR_TX_DMA_NUM =>
|
if C_DMA_EN then
|
if C_DMA_EN then
|
Sln_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0) <= opb_tx_dma_num_int;
|
Sln_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0) <= opb_tx_dma_num_int;
|
end if;
|
end if;
|
|
|
|
|
when C_ADR_RX_DMA_CTL =>
|
when C_ADR_RX_DMA_CTL =>
|
if C_DMA_EN then
|
if C_DMA_EN then
|
Sln_DBus_big_end(0 downto 0) <= opb_rx_dma_ctl_int;
|
Sln_DBus_big_end(0 downto 0) <= opb_rx_dma_ctl_int;
|
end if;
|
end if;
|
|
|
when C_ADR_RX_DMA_ADDR =>
|
when C_ADR_RX_DMA_ADDR =>
|
if C_DMA_EN then
|
if C_DMA_EN then
|
Sln_DBus_big_end(C_OPB_DWIDTH-1 downto 0) <= opb_rx_dma_addr_int;
|
Sln_DBus_big_end(C_OPB_DWIDTH-1 downto 0) <= opb_rx_dma_addr_int;
|
end if;
|
end if;
|
|
|
when C_ADR_RX_DMA_NUM =>
|
when C_ADR_RX_DMA_NUM =>
|
if C_DMA_EN then
|
if C_DMA_EN then
|
Sln_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0) <= opb_rx_dma_num_int;
|
Sln_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0) <= opb_rx_dma_num_int;
|
end if;
|
end if;
|
|
|
when C_ADR_RX_CRC =>
|
when C_ADR_RX_CRC =>
|
if C_CRC_EN then
|
if C_CRC_EN then
|
Sln_DBus_big_end(C_OPB_DWIDTH-1 downto C_SR_WIDTH) <= (others => '0');
|
Sln_DBus_big_end(C_OPB_DWIDTH-1 downto C_SR_WIDTH) <= (others => '0');
|
Sln_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_rx_crc_value;
|
Sln_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_rx_crc_value;
|
end if;
|
end if;
|
|
|
when C_ADR_TX_CRC =>
|
when C_ADR_TX_CRC =>
|
if C_CRC_EN then
|
if C_CRC_EN then
|
Sln_DBus_big_end(C_OPB_DWIDTH-1 downto C_SR_WIDTH) <= (others => '0');
|
Sln_DBus_big_end(C_OPB_DWIDTH-1 downto C_SR_WIDTH) <= (others => '0');
|
Sln_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_tx_crc_value;
|
Sln_DBus_big_end(C_SR_WIDTH-1 downto 0) <= opb_tx_crc_value;
|
end if;
|
end if;
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
else
|
else
|
-- write acess
|
-- write acess
|
case OPB_ABus_big_end(7 downto 2) is
|
case OPB_ABus_big_end(7 downto 2) is
|
when C_ADR_CTL =>
|
when C_ADR_CTL =>
|
opb_ctl_reg_int <= OPB_DBus_big_end(C_OPB_CTL_REG_WIDTH-1 downto 0);
|
opb_ctl_reg_int <= OPB_DBus_big_end(C_OPB_CTL_REG_WIDTH-1 downto 0);
|
|
|
when C_ADR_TX_DATA =>
|
when C_ADR_TX_DATA =>
|
opb_s_tx_en <= '1';
|
opb_s_tx_en <= '1';
|
opb_s_tx_data <= OPB_DBus_big_end(C_SR_WIDTH-1 downto 0);
|
opb_s_tx_data <= OPB_DBus_big_end(C_SR_WIDTH-1 downto 0);
|
|
|
when C_ADR_TX_THRESH =>
|
when C_ADR_TX_THRESH =>
|
tx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0) <= OPB_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0);
|
tx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0) <= OPB_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0);
|
tx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH) <= OPB_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16);
|
tx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH) <= OPB_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16);
|
|
|
when C_ADR_RX_THRESH =>
|
when C_ADR_RX_THRESH =>
|
rx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0) <= OPB_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0);
|
rx_thresh_int(C_FIFO_SIZE_WIDTH-1 downto 0) <= OPB_DBus_big_end(C_FIFO_SIZE_WIDTH-1 downto 0);
|
rx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH) <= OPB_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16);
|
rx_thresh_int((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH) <= OPB_DBus_big_end(16+C_FIFO_SIZE_WIDTH-1 downto 16);
|
|
|
when C_ADR_DGIE =>
|
when C_ADR_DGIE =>
|
opb_dgie_int <= OPB_DBus_big_end(0);
|
opb_dgie_int <= OPB_DBus_big_end(0);
|
|
|
when C_ADR_IER =>
|
when C_ADR_IER =>
|
opb_ier_int <= OPB_DBus_big_end(C_NUM_INT-1 downto 0);
|
opb_ier_int <= OPB_DBus_big_end(C_NUM_INT-1 downto 0);
|
|
|
when C_ADR_ISR =>
|
when C_ADR_ISR =>
|
opb_isr_clr <= OPB_DBus_big_end(C_NUM_INT-1 downto 0);
|
opb_isr_clr <= OPB_DBus_big_end(C_NUM_INT-1 downto 0);
|
|
|
when C_ADR_TX_DMA_CTL =>
|
when C_ADR_TX_DMA_CTL =>
|
if C_DMA_EN then
|
if C_DMA_EN then
|
opb_tx_dma_ctl_int <= OPB_DBus_big_end(0 downto 0);
|
opb_tx_dma_ctl_int <= OPB_DBus_big_end(0 downto 0);
|
end if;
|
end if;
|
|
|
when C_ADR_TX_DMA_ADDR =>
|
when C_ADR_TX_DMA_ADDR =>
|
if C_DMA_EN then
|
if C_DMA_EN then
|
opb_tx_dma_addr_int <= OPB_DBus_big_end(C_OPB_DWIDTH-1 downto 0);
|
opb_tx_dma_addr_int <= OPB_DBus_big_end(C_OPB_DWIDTH-1 downto 0);
|
end if;
|
end if;
|
|
|
when C_ADR_TX_DMA_NUM =>
|
when C_ADR_TX_DMA_NUM =>
|
if C_DMA_EN then
|
if C_DMA_EN then
|
opb_tx_dma_num_int <= OPB_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0);
|
opb_tx_dma_num_int <= OPB_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0);
|
end if;
|
end if;
|
|
|
when C_ADR_RX_DMA_CTL =>
|
when C_ADR_RX_DMA_CTL =>
|
if C_DMA_EN then
|
if C_DMA_EN then
|
opb_rx_dma_ctl_int <= OPB_DBus_big_end(0 downto 0);
|
opb_rx_dma_ctl_int <= OPB_DBus_big_end(0 downto 0);
|
end if;
|
end if;
|
|
|
when C_ADR_RX_DMA_ADDR =>
|
when C_ADR_RX_DMA_ADDR =>
|
if C_DMA_EN then
|
if C_DMA_EN then
|
opb_rx_dma_addr_int <= OPB_DBus_big_end(C_OPB_DWIDTH-1 downto 0);
|
opb_rx_dma_addr_int <= OPB_DBus_big_end(C_OPB_DWIDTH-1 downto 0);
|
end if;
|
end if;
|
|
|
when C_ADR_RX_DMA_NUM =>
|
when C_ADR_RX_DMA_NUM =>
|
if C_DMA_EN then
|
if C_DMA_EN then
|
opb_rx_dma_num_int <= OPB_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0);
|
opb_rx_dma_num_int <= OPB_DBus_big_end(C_WIDTH_DMA_NUM-1 downto 0);
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
end if; -- OPB_RNW
|
end if; -- OPB_RNW
|
else
|
else
|
-- not selected
|
-- not selected
|
state <= idle;
|
state <= idle;
|
end if;
|
end if;
|
when done =>
|
when done =>
|
opb_ctl_reg_int(3) <= '0';
|
opb_ctl_reg_int(3) <= '0';
|
opb_isr_clr <= (others => '0');
|
opb_isr_clr <= (others => '0');
|
opb_s_rx_en <= '0';
|
opb_s_rx_en <= '0';
|
opb_s_tx_en <= '0';
|
opb_s_tx_en <= '0';
|
Sln_xferAck <= '0';
|
Sln_xferAck <= '0';
|
Sln_DBus_big_end <= (others => '0');
|
Sln_DBus_big_end <= (others => '0');
|
state <= idle;
|
state <= idle;
|
|
|
when others =>
|
when others =>
|
state <= idle;
|
state <= idle;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process opb_slave_proc;
|
end process opb_slave_proc;
|
end behavior;
|
end behavior;
|
|
|