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Line 31... |
input wire [3:0] iId,
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input wire [3:0] iId,
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output wire [`COMMIT_PACKET_SIZE-1:0] oCommitData,
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output wire [`COMMIT_PACKET_SIZE-1:0] oCommitData,
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output wire oCommitResquest,
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output wire oCommitResquest,
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input wire iCommitGranted,
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input wire iCommitGranted,
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output wire oBusy,
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output wire oBusy,
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//OMEM
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output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress,
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output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress,
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output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData,
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output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData,
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output wire oOMEMWriteEnable
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output wire oOMEMWriteEnable,
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//TMEM
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output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadAddress, //3 * 32 addresses to read from TMEM
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input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadData, //Contains the data read from the TMEM, 3 * 32 bit words
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input wire iTMEMDataAvailable, //This is set to one once the TMEM read transaction is complete
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output wire oTMEMDataRequest //Set to one to indicate a TMEM read request
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);
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);
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wire wExeDone;
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wire wExeDone;
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wire [2:0] wExeDoneTmp;
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wire [2:0] wExeDoneTmp;
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wire wRS_OMWRITE_Trigger;
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wire wRS_OMWRITE_Trigger;
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wire [`DATA_ROW_WIDTH-1:0] wRS1_OperandA;
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wire [`DATA_ROW_WIDTH-1:0] wRS1_OperandA;
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wire [`DATA_ROW_WIDTH-1:0] wRS1_OperandB;
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wire [`DATA_ROW_WIDTH-1:0] wRS1_OperandB;
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wire [`DATA_ROW_WIDTH-1:0] wResult;
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wire wCommitGranted;
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wire wCommitGranted;
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//ReservationStation_1Cycle RS
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wire [2:0] wIOOperation;
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ReservationStation RS
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wire wIOTrigger,wIOTrigger_Pre;
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wire ReadInProgress_Delay;
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wire wExeDone_pre1,wExeDone_pre2,wExeDone_pre3,wExeDone_pre4;
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wire wCommitResquest;
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//assign oTMEMDataRequest = (wIOTrigger && wIOOperation == `IO_OPERATION_TMREAD ) ? wIOTrigger : 1'b0;
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wire ReadInProgress;
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assign ReadInProgress = (wIOOperation == `IO_OPERATION_TMREAD) ? 1'b1 : 1'b0;
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assign oTMEMDataRequest = ((wIOTrigger | ~iTMEMDataAvailable) & ReadInProgress ) ? 1'b1:1'b0;//wIOTrigger : 1'b0;
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assign oTMEMReadAddress = wRS1_OperandA; //Three separate 32 bit addresses comes here, for 3 addresses
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) WOP_FFD0 //TODO: This should be 1 bit
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( Clock, Reset, 1'b1 , wIOTrigger_Pre | wExeDone_pre1 | wExeDone_pre2, wIOTrigger );
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) WOP_CR //TODO: This should be 1 bit
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( Clock, Reset, ReadInProgress , wCommitResquest, oCommitResquest );
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///////////////////////////
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//
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// wIOOperation
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// 000 OMEM
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// 001 TMEM
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// 010 MAILBOX
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//
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///////////////////////////
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wire wBusy;
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ReservationStation_EX RS_EX
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.iIssueBus( iIssueBus ),
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.iIssueBus( iIssueBus ),
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.iCommitBus( iCommitBus ),
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.iCommitBus( iCommitBus ),
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.iMyId( iId ),
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.iMyId( iId ),
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.iExecutionDone( wExeDone ),
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.iExecutionDone( wExeDone ),
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.iResult( wResult ),
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.iResult( iTMEMReadData ),
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.iCommitGranted( wCommitGranted ),
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.iCommitGranted( wCommitGranted ),
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.oSrc1Latched( wRS1_OperandB ),
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.oSrc1Latched( wRS1_OperandB ),
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.oSrc0Latched( wRS1_OperandA ),
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.oSrc0Latched( wRS1_OperandA ),
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.oBusy( oBusy ),
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.oBusy( wBusy ),
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.oTrigger( wRS_OMWRITE_Trigger )
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.oScale( wIOOperation ),
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.oTrigger( wIOTrigger_Pre ),
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///
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.oCommitRequest( wCommitResquest ),
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.oId( oCommitData[`COMMIT_RSID_RNG] ),
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.oWE( oCommitData[`COMMIT_WE_RNG] ),
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.oDestination( oCommitData[`COMMIT_DST_RNG] ),
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.oResult( {oCommitData[`X_RNG],oCommitData[`Y_RNG],oCommitData[`Z_RNG]} )
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);
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);
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assign oBusy = (ReadInProgress)? /*oTMEMDataRequest*/ ~iTMEMDataAvailable : wBusy; /// | wIOTrigger_Pre | wExeDone_pre1 | wExeDone_pre2 | wExeDone;
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//assign oCommitResquest = 1'b0; //This is always zero since we are not writting anything into the RF
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//assign oCommitData = `COMMIT_PACKET_SIZE'd0; //This is always zero since we are not writting anything into the RF
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assign oOMEMWriteEnable = (wIOTrigger && wIOOperation == `IO_OPERATION_OMWRITE ) ? wIOTrigger : 1'b0;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 96 ) FFD_SRC0
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( Clock, Reset, wIOTrigger_Pre , wRS1_OperandA, oOMEMWriteData );
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 96 ) FFD_SRC1
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( Clock, Reset, wIOTrigger_Pre , wRS1_OperandB, oOMEMWriteAddress );
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assign oCommitResquest = 1'b0; //This is always zero since we are writting anything into the RF
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assign oCommitData = `COMMIT_PACKET_SIZE'd0; //This is always zero since we are writting anything into the RF
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//assign oOMEMWriteData = wRS1_OperandA; //Write 96 bits to external memory OMEM
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assign oOMEMWriteData = wRS1_OperandA; //Write 96 bits to external memory OMEM
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//assign oOMEMWriteAddress = wRS1_OperandB; //Each 32 bit words has the write address
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assign oOMEMWriteAddress = wRS1_OperandB; //Each 32 bit words has the write address
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD0
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD0
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( Clock, Reset, 1'b1 , wRS_OMWRITE_Trigger | wExeDone_pre1 | wExeDone_pre2, oOMEMWriteEnable );
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( Clock, Reset, 1'b1 , wIOTrigger_Pre | wExeDone_pre1 | wExeDone_pre2, wIOTrigger );
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//It takes 3 clock cycles to write the 96 bits into OMEM
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//It takes 3 clock cycles to write the 96 bits into OMEM
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wire wExeDone_pre1,wExeDone_pre2;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD1
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD1
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( Clock, Reset, 1'b1 , wRS_OMWRITE_Trigger, wExeDone_pre1 );
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( Clock, Reset, 1'b1 , wIOTrigger_Pre, wExeDone_pre1 );
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD2
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD2
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( Clock, Reset, 1'b1 , wExeDone_pre1, wExeDone_pre2 );
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( Clock, Reset, 1'b1 , wExeDone_pre1, wExeDone_pre2 );
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD3
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD3
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( Clock, Reset, 1'b1 , wExeDone_pre2, wExeDone );
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( Clock, Reset, 1'b1 , wExeDone_pre2, wExeDone_pre3 );
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD4
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( Clock, Reset, 1'b1 , wExeDone_pre3, wExeDone_pre4 );
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) DONE_FFD5
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( Clock, Reset, 1'b1 ,oTMEMDataRequest , ReadInProgress_Delay );
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assign wCommitGranted = wExeDone;
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assign wExeDone = (ReadInProgress_Delay) ? iTMEMDataAvailable : wExeDone_pre3;
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assign wCommitGranted = (ReadInProgress_Delay) ? wExeDone : wExeDone_pre4;
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//assign wCommitGranted = wExeDone;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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