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[/] [theia_gpu/] [branches/] [beta_2.0/] [rtl/] [Module_OperandModifiers.v] - Diff between revs 213 and 230

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Rev 213 Rev 230
Line 30... Line 30...
input wire [3:0]                        iRs,
input wire [3:0]                        iRs,
input wire [2:0]                        iScale,
input wire [2:0]                        iScale,
output wire [2:0]                       oScale,
output wire [2:0]                       oScale,
input wire[`ISSUE_SRCTAG_SIZE-1:0]      iTag,
input wire[`ISSUE_SRCTAG_SIZE-1:0]      iTag,
input wire[`COMMIT_PACKET_SIZE-1:0]     iData,
input wire[`COMMIT_PACKET_SIZE-1:0]     iData,
output wire[`COMMIT_PACKET_SIZE-1:0]    oData,
output wire[`DATA_ROW_WIDTH-1:0]        oData,
output wire[3:0]                        oRsID,
output wire[3:0]                        oRsID,
input wire[3:0]                         iKey,
input wire[3:0]                         iKey,
output wire                             oRequest,
output wire                             oRequest,
output wire                             oBusy,
output wire                             oBusy,
output wire[`ISSUE_SRCTAG_SIZE-1:0]     oTag
output wire[`ISSUE_SRCTAG_SIZE-1:0]     oTag
Line 74... Line 74...
//20 DST, SWZZL 6 bits, SCALE 3 bits, SIGN 3 bits = 15
//20 DST, SWZZL 6 bits, SCALE 3 bits, SIGN 3 bits = 15
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `ISSUE_SRCTAG_SIZE ) FFD1
FFD_POSEDGE_SYNCRONOUS_RESET # ( `ISSUE_SRCTAG_SIZE ) FFD1
(       Clock, Reset, iKeep ,iTag  , oTag  );
(       Clock, Reset, iKeep ,iTag  , oTag  );
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `COMMIT_PACKET_SIZE ) FFD2
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD2
(       Clock, Reset, wMatch ,iData  , oData  );
(       Clock, Reset, wMatch ,iData[`DATA_ROW_WIDTH-1:0]  , oData  );
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD3
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD3
(       Clock, Reset, iKeep ,iRs  , oRsID  );
(       Clock, Reset, iKeep ,iRs  , oRsID  );
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( 3 ) FFD4
FFD_POSEDGE_SYNCRONOUS_RESET # ( 3 ) FFD4
Line 353... Line 353...
 
 
);
);
 
 
 
 
wire[3:0] wBusSelector;
wire[3:0] wBusSelector;
DECODER_ONEHOT_2_BINARY DECODER
DECODER_ONEHOT_2_BINARY # (.OUTPUT_WIDTH(4) )DECODER
(
(
.iIn( {1'b0,wGranted} ),
.iIn( {2'b0,wGranted}      ),
.oOut( wBusSelector        )
.oOut( wBusSelector        )
);
);
 
 
MUXFULLPARALELL_3SEL_GENERIC # (`ISSUE_SRCTAG_SIZE + `DATA_ROW_WIDTH ) MUX
MUXFULLPARALELL_3SEL_GENERIC # (`ISSUE_SRCTAG_SIZE + `DATA_ROW_WIDTH ) MUX
 (
 (
 .Sel(wBusSelector),
 .Sel( wBusSelector[2:0]                                                     ),
 .I1( {`ISSUE_SRCTAG_SIZE'b0,`DATA_ROW_WIDTH'b0}  ),
 .I1( {`ISSUE_SRCTAG_SIZE'b0,`DATA_ROW_WIDTH'b0}  ),
 .I2( {wIssueBus[`ISSUE_SRC0_TAG_RNG],wIssueBus[`ISSUE_SRC0_DATA_RNG]} ),
 .I2( {wIssueBus[`ISSUE_SRC0_TAG_RNG],wIssueBus[`ISSUE_SRC0_DATA_RNG]} ),
 .I3(  {wOutTag0,wData0} ),
 .I3(  {wOutTag0,wData0} ),
 .I4(  {wOutTag1,wData1} ),
 .I4(  {wOutTag1,wData1} ),
 .I5(  {wOutTag2,wData2} ),
 .I5(  {wOutTag2,wData2} ),
Line 373... Line 373...
 .O1( wSrcA_Pre )
 .O1( wSrcA_Pre )
 );
 );
 
 
 MUXFULLPARALELL_3SEL_GENERIC # ( 4 ) MUX2
 MUXFULLPARALELL_3SEL_GENERIC # ( 4 ) MUX2
 (
 (
 .Sel(wBusSelector),
 .Sel(wBusSelector[2:0] ),
 .I1( 4'b0  ),
 .I1( 4'b0  ),
 .I2( 4'b0  ),
 .I2( 4'b0  ),
 .I3(  wOutRs0 ),
 .I3(  wOutRs0 ),
 .I4(  wOutRs1 ),
 .I4(  wOutRs1 ),
 .I5(  wOutRs2 ),
 .I5(  wOutRs2 ),
Line 386... Line 386...
 );
 );
 
 
 
 
 MUXFULLPARALELL_3SEL_GENERIC # ( 3 ) MUX3
 MUXFULLPARALELL_3SEL_GENERIC # ( 3 ) MUX3
 (
 (
 .Sel(wBusSelector),
 .Sel( wBusSelector[2:0] ),
 .I1( 3'b0  ),
 .I1( 3'b0  ),
 .I2( 3'b0  ),
 .I2( 3'b0  ),
 .I3(  wOutScale0 ),
 .I3(  wOutScale0 ),
 .I4(  wOutScale1 ),
 .I4(  wOutScale1 ),
 .I5(  wOutScale2 ),
 .I5(  wOutScale2 ),

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