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[/] [theia_gpu/] [branches/] [beta_2.0/] [rtl/] [Module_RadixRMul.v] - Diff between revs 213 and 230
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Rev 230 |
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Line 66... |
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire[31:0] A,
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input wire[31:0] A,
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input wire[31:0] B,
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input wire[31:0] B,
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output wire[63:0] R,
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output wire[31:0] R, //Warning, this sould be 64 bis as in Theia v1.0, I am loosing lots of precision in here!
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input wire iUnscaled,
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input wire iUnscaled,
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input wire iInputReady,
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input wire iInputReady,
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output wire OutputReady
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output wire OutputReady
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assign R_pre1 = (iUnscaled == 1) ? (wPartialResult3_0 + wPartialResult3_1) : ((wPartialResult3_0 + wPartialResult3_1) >> `SCALE);
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assign R_pre1 = (iUnscaled == 1) ? (wPartialResult3_0 + wPartialResult3_1) : ((wPartialResult3_0 + wPartialResult3_1) >> `SCALE);
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assign R_pre2 = ( (SignA ^ SignB) == 1) ? ~R_pre1 + 1'b1 : R_pre1;
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assign R_pre2 = ( (SignA ^ SignB) == 1) ? ~R_pre1 + 1'b1 : R_pre1;
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//assign R = R_pre2 >> `SCALE;
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//assign R = R_pre2 >> `SCALE;
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assign R = R_pre2;
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assign R = R_pre2[31:0];
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endmodule
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endmodule
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