| Line 27... |
Line 27... |
input wire Reset,
|
input wire Reset,
|
input wire iEnable,
|
input wire iEnable,
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input wire [`INSTRUCTION_ADDR_WIDTH-1:0] iInstructionMem_WriteAddress,
|
input wire [`INSTRUCTION_ADDR_WIDTH-1:0] iInstructionMem_WriteAddress,
|
input wire iInstructionMem_WriteEnable,
|
input wire iInstructionMem_WriteEnable,
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input wire [`INSTRUCTION_WIDTH-1:0] iInstructionMem_WriteData,
|
input wire [`INSTRUCTION_WIDTH-1:0] iInstructionMem_WriteData,
|
|
//OMEM
|
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress,
|
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress,
|
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData,
|
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData,
|
output wire oOMEMWriteEnable
|
output wire oOMEMWriteEnable,
|
|
//TMEM
|
|
output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadAddress,
|
|
input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadData,
|
|
input wire iTMEMDataAvailable,
|
|
output wire oTMEMDataRequest
|
);
|
);
|
|
|
wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII_2_IM_IP0;
|
wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII_2_IM_IP0;
|
wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII_2_IM_IP1;
|
wire [`INSTRUCTION_ADDR_WIDTH -1:0] wII_2_IM_IP1;
|
wire [`INSTRUCTION_WIDTH-1:0] wIM_2_II_Instruction0;
|
wire [`INSTRUCTION_WIDTH-1:0] wIM_2_II_Instruction0;
|
| Line 42... |
Line 47... |
wire [`DATA_ADDRESS_WIDTH-1:0] wII_2_RF_Addr0;
|
wire [`DATA_ADDRESS_WIDTH-1:0] wII_2_RF_Addr0;
|
wire [`DATA_ADDRESS_WIDTH-1:0] wII_2_RF_Addr1;
|
wire [`DATA_ADDRESS_WIDTH-1:0] wII_2_RF_Addr1;
|
wire [`DATA_ROW_WIDTH-1:0] wRF_2_II_Data0;
|
wire [`DATA_ROW_WIDTH-1:0] wRF_2_II_Data0;
|
wire [`DATA_ROW_WIDTH-1:0] wRF_2_II_Data1;
|
wire [`DATA_ROW_WIDTH-1:0] wRF_2_II_Data1;
|
wire [`NUMBER_OF_RSVR_STATIONS-1:0] wRS_2_II_Busy;
|
wire [`NUMBER_OF_RSVR_STATIONS-1:0] wRS_2_II_Busy;
|
wire [`ISSUE_PACKET_SIZE-1:0] wIssueBus,wModIssue;
|
wire [`ISSUE_PACKET_SIZE-1:0] wIssueBus;
|
|
wire [`MOD_ISSUE_PACKET_SIZE-1:0] wModIssue;
|
wire [`NUMBER_OF_RSVR_STATIONS-1:0] wStationCommitRequest;
|
wire [`NUMBER_OF_RSVR_STATIONS-1:0] wStationCommitRequest;
|
wire [`NUMBER_OF_RSVR_STATIONS-1:0] wStationCommitGrant;
|
wire [`NUMBER_OF_RSVR_STATIONS-1:0] wStationCommitGrant;
|
wire [`COMMIT_PACKET_SIZE-1:0] wCommitBus;
|
wire [`COMMIT_PACKET_SIZE-1:0] wCommitBus;
|
wire [`MOD_COMMIT_PACKET_SIZE-1:0] wModCommitBus;
|
wire [`MOD_COMMIT_PACKET_SIZE-1:0] wModCommitBus;
|
wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Adder0;
|
wire [`COMMIT_PACKET_SIZE-1:0] wCommitData_Adder0;
|
| Line 326... |
Line 332... |
.iCommitBus( wModCommitBus ),
|
.iCommitBus( wModCommitBus ),
|
.oCommitData( wCommitData_IO ),
|
.oCommitData( wCommitData_IO ),
|
.oCommitResquest( wStationCommitRequest[6] ),
|
.oCommitResquest( wStationCommitRequest[6] ),
|
.iCommitGranted( wStationCommitGrant[6] ),
|
.iCommitGranted( wStationCommitGrant[6] ),
|
.oBusy( wRS_2_II_Busy[6] ),
|
.oBusy( wRS_2_II_Busy[6] ),
|
|
//OMEM
|
.oOMEMWriteAddress( oOMEMWriteAddress ),
|
.oOMEMWriteAddress( oOMEMWriteAddress ),
|
.oOMEMWriteData( oOMEMWriteData ),
|
.oOMEMWriteData( oOMEMWriteData ),
|
.oOMEMWriteEnable( oOMEMWriteEnable )
|
.oOMEMWriteEnable( oOMEMWriteEnable ),
|
|
//TMEM
|
|
.oTMEMReadAddress( oTMEMReadAddress ),
|
|
.iTMEMReadData( iTMEMReadData ),
|
|
.iTMEMDataAvailable( iTMEMDataAvailable ),
|
|
.oTMEMDataRequest( oTMEMDataRequest )
|
|
|
);
|
);
|
|
|
ROUND_ROBIN_7_ENTRIES ARB
|
ROUND_ROBIN_7_ENTRIES ARB
|
//ROUND_ROBIN_6_ENTRIES ARB
|
//ROUND_ROBIN_6_ENTRIES ARB
|
| Line 354... |
Line 366... |
.oGrant5( wStationCommitGrant[5] ),
|
.oGrant5( wStationCommitGrant[5] ),
|
.oGrant6( wStationCommitGrant[6] )
|
.oGrant6( wStationCommitGrant[6] )
|
|
|
);
|
);
|
|
|
|
wire [5:0] wBusSelector_Tmp;
|
wire[3:0] wBusSelector;
|
wire[2:0] wBusSelector;
|
DECODER_ONEHOT_2_BINARY DECODER
|
DECODER_ONEHOT_2_BINARY DECODER
|
(
|
(
|
.iIn( wStationCommitGrant ),
|
.iIn( wStationCommitGrant ),
|
.oOut( wBusSelector )
|
.oOut( wBusSelector_Tmp )
|
);
|
);
|
|
assign wBusSelector = wBusSelector_Tmp[3:0];
|
|
|
|
MUXFULLPARALELL_3SEL_GENERIC # (`COMMIT_PACKET_SIZE ) MUX //TODO I need one more entry for the IO
|
MUXFULLPARALELL_3SEL_GENERIC # (`COMMIT_PACKET_SIZE ) MUX
|
|
(
|
(
|
.Sel(wBusSelector),
|
.Sel(wBusSelector),
|
.I1(`COMMIT_PACKET_SIZE'b0),
|
.I1(`COMMIT_PACKET_SIZE'b0),
|
.I2(wCommitData_Adder0),
|
.I2(wCommitData_Adder0),
|
.I3(wCommitData_Adder1),
|
.I3(wCommitData_Adder1),
|
.I4(wCommitData_Div),
|
.I4(wCommitData_Div),
|
.I5(wCommitData_Mul),
|
.I5(wCommitData_Mul),
|
.I6(wCommitData_Sqrt),
|
.I6(wCommitData_Sqrt),
|
.I7(wCommitData_Logic),
|
.I7(wCommitData_Logic),
|
|
.I8(wCommitData_IO ),
|
.O1(wCommitBus)
|
.O1(wCommitBus)
|
);
|
);
|
|
|
|
|
endmodule
|
endmodule
|
