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https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk
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Rev 230 |
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input wire [`DATA_ROW_WIDTH-1:0] iOMEM_WriteAddress,
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input wire [`DATA_ROW_WIDTH-1:0] iOMEM_WriteAddress,
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input wire [`DATA_ROW_WIDTH-1:0] iOMEM_WriteData,
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input wire [`DATA_ROW_WIDTH-1:0] iOMEM_WriteData,
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input wire iOMEM_WriteEnable,
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input wire iOMEM_WriteEnable,
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output wire [`WB_WIDTH-1:0] OMEM_DAT_O,
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output wire [`WB_WIDTH-1:0] OMEM_DAT_O,
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output wire [`WB_WIDTH-1:0] OMEM_ADR_O,
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output wire [`WB_WIDTH-1:0] OMEM_ADR_O,
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output wire OMEM_WE_O
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output wire OMEM_WE_O,
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//TMem
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output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadData,
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input wire iTMEMDataRequest,
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input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadAddress,
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output wire oTMEMDataAvailable,
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input wire TMEM_ACK_I,
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input wire [`WB_WIDTH-1:0] TMEM_DAT_I ,
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output wire [`WB_WIDTH-1:0] TMEM_ADR_O ,
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output wire TMEM_WE_O,
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output wire TMEM_STB_O,
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output wire TMEM_CYC_O,
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input wire TMEM_GNT_I
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);
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);
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WishBoneSlaveUnit WBS
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WishBoneSlaveUnit WBS
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);
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);
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Module_TMemInterface TMI
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(
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.Clock( CLK_I ),
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.Reset( RST_I ),
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.iEnable( iTMEMDataRequest ),
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.iAddress( iTMEMReadAddress ),
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.oData( oTMEMReadData ),
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.oDone( oTMEMDataAvailable ),
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.ACK_I( TMEM_ACK_I ),
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.GNT_I( TMEM_GNT_I ),
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.DAT_I( TMEM_DAT_I ),
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.ADR_O( TMEM_ADR_O ),
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.WE_O( TMEM_WE_O ),
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.STB_O( TMEM_STB_O ),
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.CYC_O( TMEM_CYC_O )
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);
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endmodule
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endmodule
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