/*
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/*
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* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
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* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
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*
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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* You may obtain a copy of the License at
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*
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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*
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* Unless required by applicable law or agreed to in writing, software
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* See the License for the specific language governing permissions and
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* limitations under the License.
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* limitations under the License.
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*/
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*/
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/* FSM: finite state machine
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/* FSM: finite state machine
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* halt if $ctrl == 0$
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* halt if $ctrl == 0$
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*/
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*/
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module FSM(clk, reset, rom_addr, rom_q, ram_a_addr, ram_b_addr, ram_b_w, pe, done);
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module FSM(clk, reset, rom_addr, rom_q, ram_a_addr, ram_b_addr, ram_b_w, pe, done);
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input clk;
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input clk;
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input reset;
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input reset;
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output reg [8:0] rom_addr; /* command id. extra bits? */
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output reg [8:0] rom_addr; /* command id. extra bits? */
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input [25:0] rom_q; /* command value */
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input [25:0] rom_q; /* command value */
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output reg [5:0] ram_a_addr;
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output reg [5:0] ram_a_addr;
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output reg [5:0] ram_b_addr;
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output reg [5:0] ram_b_addr;
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output ram_b_w;
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output ram_b_w;
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output reg [10:0] pe;
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output reg [10:0] pe;
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output reg done;
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output reg done;
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reg [4:0] state;
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reg [5:0] state;
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parameter START=0, READ_SRC1=1, READ_SRC2=2, CALC=4, WAIT=8, WRITE=16, DON=3;
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parameter START=0, READ_SRC1=1, READ_SRC2=2, CALC=4, WAIT=8, WRITE=16, DON=32;
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wire [5:0] dest, src1, src2, times; wire [1:0] op;
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wire [5:0] dest, src1, src2, times; wire [1:0] op;
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assign {dest, src1, op, times, src2} = rom_q;
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assign {dest, src1, op, times, src2} = rom_q;
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reg [5:0] count;
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reg [5:0] count;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset)
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if (reset)
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state<=START;
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state<=START;
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else
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else
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case (state)
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case (state)
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START:
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START:
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state<=READ_SRC1;
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state<=READ_SRC1;
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READ_SRC1:
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READ_SRC1:
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state<=READ_SRC2;
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state<=READ_SRC2;
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READ_SRC2:
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READ_SRC2:
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if (times==0) state<=DON; else state<=CALC;
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if (times==0) state<=DON; else state<=CALC;
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CALC:
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CALC:
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if (count==1) state<=WAIT;
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if (count==1) state<=WAIT;
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WAIT:
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WAIT:
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state<=WRITE;
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state<=WRITE;
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WRITE:
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WRITE:
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state<=READ_SRC1;
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state<=READ_SRC1;
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endcase
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endcase
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/* we support two loops with 48 loop times */
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/* we support two loops with 48 loop times */
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parameter LOOP1_START = 9'd22,
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parameter LOOP1_START = 9'd22,
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LOOP1_END = 9'd117,
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LOOP1_END = 9'd117,
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LOOP2_START = 9'd280,
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LOOP2_START = 9'd280,
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LOOP2_END = 9'd293;
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LOOP2_END = 9'd293;
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reg [46:0] loop1, loop2;
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reg [46:0] loop1, loop2;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) rom_addr<=0;
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if (reset) rom_addr<=0;
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else if (state==WAIT)
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else if (state==WAIT)
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begin
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begin
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if(rom_addr == LOOP1_END && loop1[0])
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if(rom_addr == LOOP1_END && loop1[0])
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rom_addr <= LOOP1_START;
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rom_addr <= LOOP1_START;
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else if(rom_addr == LOOP2_END && loop2[0])
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else if(rom_addr == LOOP2_END && loop2[0])
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rom_addr <= LOOP2_START;
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rom_addr <= LOOP2_START;
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else
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else
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rom_addr <= rom_addr + 1;
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rom_addr <= rom_addr + 1;
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) loop1 <= ~0;
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if (reset) loop1 <= ~0;
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else if(state==WAIT && rom_addr==LOOP1_END)
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else if(state==WAIT && rom_addr==LOOP1_END)
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loop1 <= loop1 >> 1;
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loop1 <= loop1 >> 1;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) loop2 <= ~0;
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if (reset) loop2 <= ~0;
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else if(state==WAIT && rom_addr==LOOP2_END)
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else if(state==WAIT && rom_addr==LOOP2_END)
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loop2 <= loop2 >> 1;
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loop2 <= loop2 >> 1;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset)
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if (reset)
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count<=0;
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count<=0;
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else if (state==READ_SRC1)
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else if (state==READ_SRC1)
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count<=times;
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count<=times;
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else if (state==CALC)
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else if (state==CALC)
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count<=count-1;
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count<=count-1;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset) done<=0;
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if (reset) done<=0;
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else if (state==DON) done<=1;
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else if (state==DON) done<=1;
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else done<=0;
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else done<=0;
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always @ (state, src1, src2)
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always @ (state, src1, src2)
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case (state)
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case (state)
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READ_SRC1: ram_a_addr=src1;
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READ_SRC1: ram_a_addr=src1;
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READ_SRC2: ram_a_addr=src2;
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READ_SRC2: ram_a_addr=src2;
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default: ram_a_addr=0;
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default: ram_a_addr=0;
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endcase
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endcase
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parameter CMD_ADD=6'd4, CMD_SUB=6'd8, CMD_CUBIC=6'd16,
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parameter CMD_ADD=6'd4, CMD_SUB=6'd8, CMD_CUBIC=6'd16,
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ADD=2'd0, SUB=2'd1, CUBIC=2'd2, MULT=2'd3;
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ADD=2'd0, SUB=2'd1, CUBIC=2'd2, MULT=2'd3;
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always @ (posedge clk)
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always @ (posedge clk)
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case (state)
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case (state)
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READ_SRC1:
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READ_SRC1:
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case (op)
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case (op)
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ADD: pe<=11'b11001000000;
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ADD: pe<=11'b11001000000;
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SUB: pe<=11'b11001000000;
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SUB: pe<=11'b11001000000;
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CUBIC: pe<=11'b11111000000;
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CUBIC: pe<=11'b11111000000;
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MULT: pe<=11'b11110000000;
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MULT: pe<=11'b11110000000;
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default: pe<=0;
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default: pe<=0;
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endcase
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endcase
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READ_SRC2:
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READ_SRC2:
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case (op)
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case (op)
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ADD: pe<=11'b00110000000;
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ADD: pe<=11'b00110000000;
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SUB: pe<=11'b00110000000;
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SUB: pe<=11'b00110000000;
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CUBIC: pe<=0;
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CUBIC: pe<=0;
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MULT: pe<=11'b00001000000;
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MULT: pe<=11'b00001000000;
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default: pe<=0;
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default: pe<=0;
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endcase
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endcase
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CALC:
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CALC:
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case (op)
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case (op)
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ADD: pe<=11'b00000010001;
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ADD: pe<=11'b00000010001;
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SUB: pe<=11'b00000010001;
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SUB: pe<=11'b00000010001;
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CUBIC: pe<=11'b01010000001;
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CUBIC: pe<=11'b01010000001;
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MULT: pe<=11'b00000111111;
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MULT: pe<=11'b00000111111;
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default: pe<=0;
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default: pe<=0;
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endcase
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endcase
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default:
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default:
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pe<=0;
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pe<=0;
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endcase
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endcase
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always @ (state, op, src2, dest)
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always @ (state, op, src2, dest)
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case (state)
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case (state)
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READ_SRC1:
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READ_SRC1:
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case (op)
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case (op)
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ADD: ram_b_addr=CMD_ADD;
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ADD: ram_b_addr=CMD_ADD;
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SUB: ram_b_addr=CMD_SUB;
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SUB: ram_b_addr=CMD_SUB;
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CUBIC: ram_b_addr=CMD_CUBIC;
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CUBIC: ram_b_addr=CMD_CUBIC;
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default: ram_b_addr=0;
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default: ram_b_addr=0;
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endcase
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endcase
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READ_SRC2: ram_b_addr=src2;
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READ_SRC2: ram_b_addr=src2;
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WRITE: ram_b_addr=dest;
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WRITE: ram_b_addr=dest;
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default: ram_b_addr=0;
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default: ram_b_addr=0;
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endcase
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endcase
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assign ram_b_w = (state==WRITE) ? 1'b1 : 1'b0;
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assign ram_b_w = (state==WRITE) ? 1'b1 : 1'b0;
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endmodule
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endmodule
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