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-----------------------------------------------------------------------------------------
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-- baud rate generator for uart
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-- baud rate generator for uart
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--
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--
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-- this module has been changed to receive the baud rate dividing counter from registers.
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-- this module has been changed to receive the baud rate dividing counter from registers.
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-- the two registers should be calculated as follows:
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-- the two registers should be calculated as follows:
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-- first register:
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-- first register:
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-- baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
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-- baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
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-- second register:
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-- second register:
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-- baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq
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-- baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq
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--
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--
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-----------------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity baudGen is
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entity baudGen is
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port ( clr : in std_logic; -- global reset input
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port ( clr : in std_logic; -- global reset input
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clk : in std_logic; -- global clock input
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clk : in std_logic; -- global clock input
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-- baudFreq = 16 * baudRate / gcd(clkFreq, 16 * baudRate)
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-- baudFreq = 16 * baudRate / gcd(clkFreq, 16 * baudRate)
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baudFreq : in std_logic_vector(11 downto 0); -- baud rate setting registers - see header description
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baudFreq : in std_logic_vector(11 downto 0); -- baud rate setting registers - see header description
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-- baudLimit = clkFreq / gcd(clkFreq, 16 * baudRate) - baudFreq
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-- baudLimit = clkFreq / gcd(clkFreq, 16 * baudRate) - baudFreq
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baudLimit : in std_logic_vector(15 downto 0); -- baud rate setting registers - see header description
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baudLimit : in std_logic_vector(15 downto 0); -- baud rate setting registers - see header description
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ce16 : out std_logic); -- baud rate multiplyed by 16
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ce16 : out std_logic); -- baud rate multiplyed by 16
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end baudGen;
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end baudGen;
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architecture Behavioral of baudGen is
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architecture Behavioral of baudGen is
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signal counter : std_logic_vector(15 downto 0);
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signal counter : std_logic_vector(15 downto 0);
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begin
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begin
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-- baud divider counter
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-- baud divider counter
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-- clock divider output
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-- clock divider output
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process (clr, clk)
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process (clr, clk)
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begin
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begin
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if (clr = '1') then
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if (clr = '1') then
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counter <= (others => '0');
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counter <= (others => '0');
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ce16 <= '0';
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ce16 <= '0';
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elsif (rising_edge(clk)) then
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elsif (rising_edge(clk)) then
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if (counter >= baudLimit) then
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if (counter >= baudLimit) then
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counter <= counter - baudLimit;
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counter <= std_logic_vector(unsigned(counter) - unsigned(baudLimit));
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ce16 <= '1';
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ce16 <= '1';
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else
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else
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counter <= counter + baudFreq;
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counter <= std_logic_vector(unsigned(counter) + unsigned(baudFreq));
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ce16 <= '0';
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ce16 <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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