/*!
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/*!
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intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15b
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intraffic -- example showing how the EZ-USB FIFO interface is used on ZTEX USB-FPGA Module 1.15b
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Copyright (C) 2009-2011 ZTEX GmbH.
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Copyright (C) 2009-2014 ZTEX GmbH.
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http://www.ztex.de
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http://www.ztex.de
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 3 as
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it under the terms of the GNU General Public License version 3 as
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published by the Free Software Foundation.
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, see http://www.gnu.org/licenses/.
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along with this program; if not, see http://www.gnu.org/licenses/.
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!*/
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!*/
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#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros
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#include[ztex-conf.h] // Loads the configuration macros, see ztex-conf.h for the available macros
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#include[ztex-utils.h] // include basic functions
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#include[ztex-utils.h] // include basic functions
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// configure endpoint 2, in, quad buffered, 512 bytes, interface 0
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// configure endpoint 2, in, quad buffered, 512 bytes, interface 0
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EP_CONFIG(2,0,BULK,IN,512,4);
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EP_CONFIG(2,0,BULK,IN,512,4);
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// configure endpoint 6, out, doublebuffered, 512 bytes, interface 0
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// configure endpoint 6, out, doublebuffered, 512 bytes, interface 0
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EP_CONFIG(6,0,BULK,OUT,512,2);
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EP_CONFIG(6,0,BULK,OUT,512,2);
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// select ZTEX USB FPGA Module 1.15 as target (required for FPGA configuration)
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// select ZTEX USB FPGA Module 1.15 as target (required for FPGA configuration)
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IDENTITY_UFM_1_15(10.13.0.0,0);
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IDENTITY_UFM_1_15(10.13.0.0,0);
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ENABLE_UFM_1_15X_DETECTION; // avoids some warnings
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ENABLE_UFM_1_15X_DETECTION; // avoids some warnings
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// this product string is also used for identification by the host software
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// this product string is also used for identification by the host software
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#define[PRODUCT_STRING]["intraffic example for UFM 1.15"]
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#define[PRODUCT_STRING]["intraffic example for UFM 1.15"]
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// enables high speed FPGA configuration via EP6
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// enables high speed FPGA configuration via EP6
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ENABLE_HS_FPGA_CONF(6);
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ENABLE_HS_FPGA_CONF(6);
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// this is called automatically after FPGA configuration
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// this is called automatically after FPGA configuration
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#define[POST_FPGA_CONFIG][POST_FPGA_CONFIG
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#define[POST_FPGA_CONFIG][POST_FPGA_CONFIG
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IOA7 = 1; // reset on
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IOA7 = 1; // reset on
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OEA |= bmBIT7;
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OEA |= bmBIT7;
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IOC0 = 0; // controlled mode
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IOC0 = 0; // controlled mode
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OEC = 1;
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OEC = 1;
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EP2CS &= ~bmBIT0; // clear stall bit
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EP2CS &= ~bmBIT0; // clear stall bit
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REVCTL = 0x3;
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REVCTL = 0x3;
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SYNCDELAY;
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SYNCDELAY;
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IFCONFIG = bmBIT7 | bmBIT5 | 3; // internel 30MHz clock, drive IFCLK ouput, slave FIFO interface
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IFCONFIG = bmBIT7 | bmBIT5 | 3; // internel 30MHz clock, drive IFCLK ouput, slave FIFO interface
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SYNCDELAY;
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SYNCDELAY;
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EP2FIFOCFG = bmBIT3 | bmBIT0; // AOTUOIN, WORDWIDE
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EP2FIFOCFG = bmBIT3 | bmBIT0; // AOTUOIN, WORDWIDE
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SYNCDELAY;
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SYNCDELAY;
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#ifdef[fastmode]
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#ifdef[fastmode]
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EP2AUTOINLENH = 4; // 1024 bytes
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EP2AUTOINLENH = 4; // 1024 bytes
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#else
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#else
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EP2AUTOINLENH = 2; // 512 bytes
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EP2AUTOINLENH = 2; // 512 bytes
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#endif
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#endif
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SYNCDELAY;
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SYNCDELAY;
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EP2AUTOINLENL = 0;
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EP2AUTOINLENL = 0;
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SYNCDELAY;
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SYNCDELAY;
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FIFORESET = 0x80; // reset FIFO
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FIFORESET = 0x80; // reset FIFO
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SYNCDELAY;
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SYNCDELAY;
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FIFORESET = 2;
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FIFORESET = 2;
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SYNCDELAY;
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SYNCDELAY;
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FIFORESET = 0x00;
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FIFORESET = 0x00;
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SYNCDELAY;
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SYNCDELAY;
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FIFOPINPOLAR = 0;
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FIFOPINPOLAR = 0;
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SYNCDELAY;
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SYNCDELAY;
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PINFLAGSAB = 0;
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PINFLAGSAB = 0;
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SYNCDELAY;
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SYNCDELAY;
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PINFLAGSCD = 0;
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PINFLAGSCD = 0;
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SYNCDELAY;
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SYNCDELAY;
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IOA7 = 0; // reset off
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IOA7 = 0; // reset off
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]
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]
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// set mode
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// set mode
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ADD_EP0_VENDOR_COMMAND((0x60,,
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ADD_EP0_VENDOR_COMMAND((0x60,,
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IOA7 = 1; // reset on
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IOA7 = 1; // reset on
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IOC0 = SETUPDAT[2] ? 1 : 0;
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IOC0 = SETUPDAT[2] ? 1 : 0;
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IOA7 = 0; // reset off
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IOA7 = 0; // reset off
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,,
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,,
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NOP;
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NOP;
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));;
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));;
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// include the main part of the firmware kit, define the descriptors, ...
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// include the main part of the firmware kit, define the descriptors, ...
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#include[ztex.h]
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#include[ztex.h]
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void main(void)
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void main(void)
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{
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{
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init_USB();
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init_USB();
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while (1) {
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while (1) {
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}
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}
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}
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}
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