/*!
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/*!
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ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
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ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
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Copyright (C) 2009-2011 ZTEX GmbH.
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Copyright (C) 2009-2014 ZTEX GmbH.
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http://www.ztex.de
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http://www.ztex.de
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 3 as
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it under the terms of the GNU General Public License version 3 as
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published by the Free Software Foundation.
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, see http://www.gnu.org/licenses/.
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along with this program; if not, see http://www.gnu.org/licenses/.
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!*/
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!*/
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/*
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/*
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FPGA support for ZTEX USB FPGA Modules 2.13 and 2.16
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FPGA support for ZTEX USB FPGA Modules 2.13 and 2.16
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*/
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*/
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#ifndef[ZTEX_FPGA_H]
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#ifndef[ZTEX_FPGA_H]
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#define[ZTEX_FPGA_H]
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#define[ZTEX_FPGA_H]
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#define[@CAPABILITY_FPGA;]
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#define[@CAPABILITY_FPGA;]
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__xdata BYTE fpga_checksum; // checksum
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__xdata BYTE fpga_checksum; // checksum
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__xdata DWORD fpga_bytes; // transfered bytes
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__xdata DWORD fpga_bytes; // transfered bytes
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__xdata BYTE fpga_init_b; // init_b state (should be 222 after configuration)
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__xdata BYTE fpga_init_b; // init_b state (should be 222 after configuration)
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__xdata BYTE fpga_flash_result; // result of automatic fpga configuarion from Flash
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__xdata BYTE fpga_flash_result; // result of automatic fpga configuarion from Flash
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__xdata BYTE fpga_conf_initialized; // 123 if initialized
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__xdata BYTE fpga_conf_initialized; // 123 if initialized
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__xdata BYTE OOEC;
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__xdata BYTE OOEC;
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/* *********************************************************************
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/* *********************************************************************
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***** reset_fpga ****************************************************
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***** reset_fpga ****************************************************
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********************************************************************* */
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********************************************************************* */
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static void reset_fpga () {
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static void reset_fpga () {
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OEE = bmBIT7;
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OEE = bmBIT7;
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IOE = 0;
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IOE = 0;
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wait(1);
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wait(1);
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OEE = 0;
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OEE = 0;
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fpga_conf_initialized = 0;
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fpga_conf_initialized = 0;
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** init_fpga *****************************************************
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***** init_fpga *****************************************************
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********************************************************************* */
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********************************************************************* */
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static void init_fpga () {
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static void init_fpga () {
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if ( (IOE & bmBIT0) == 0 ) {
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if ( (IOE & bmBIT0) == 0 ) {
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// ensure that FPGA is in a proper configuration mode
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// ensure that FPGA is in a proper configuration mode
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OEE = bmBIT7;
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OEE = bmBIT7;
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IOE = 0;
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IOE = 0;
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wait(1);
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wait(1);
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}
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}
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OEE = 0;
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OEE = 0;
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fpga_conf_initialized = 0;
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fpga_conf_initialized = 0;
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** init_fpga_configuration ***************************************
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***** init_fpga_configuration ***************************************
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********************************************************************* */
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********************************************************************* */
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static void init_fpga_configuration () {
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static void init_fpga_configuration () {
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unsigned short k;
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unsigned short k;
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{
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{
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PRE_FPGA_RESET
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PRE_FPGA_RESET
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}
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}
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IFCONFIG = bmBIT7;
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IFCONFIG = bmBIT7;
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SYNCDELAY;
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SYNCDELAY;
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PORTCCFG = 0;
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PORTCCFG = 0;
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PORTECFG = 0;
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PORTECFG = 0;
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OOEC = OEC;
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OOEC = OEC;
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fpga_conf_initialized = 123;
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fpga_conf_initialized = 123;
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OEC &= ~( bmBIT7 | bmBIT4); // in: MOSI, MISO
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OEC &= ~( bmBIT7 | bmBIT4); // in: MOSI, MISO
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OEC |= bmBIT6; // out: CCLK
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OEC |= bmBIT6; // out: CCLK
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IOC6 = 1;
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IOC6 = 1;
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// in: INIT_B DONE
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// in: INIT_B DONE
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// OEE &= ~( bmBIT1 | bmBIT0 );
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// OEE &= ~( bmBIT1 | bmBIT0 );
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// out: CM0 CM1 RESET_N CSI RDWR
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// out: CM0 CM1 RESET_N CSI RDWR
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OEE = bmBIT3 | bmBIT4 | bmBIT7 | bmBIT2 | bmBIT5;
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OEE = bmBIT3 | bmBIT4 | bmBIT7 | bmBIT2 | bmBIT5;
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IOE = bmBIT3;
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IOE = bmBIT3;
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wait(2);
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wait(2);
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IOE = bmBIT3 | bmBIT7; // ready for configuration
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IOE = bmBIT3 | bmBIT7; // ready for configuration
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IOC6 = 0;
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IOC6 = 0;
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k=0;
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k=0;
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while (!(IOE & bmBIT1) && k<65535)
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while (!(IOE & bmBIT1) && k<65535)
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k++;
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k++;
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fpga_init_b = (IOE & bmBIT1) ? 200 : 100;
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fpga_init_b = (IOE & bmBIT1) ? 200 : 100;
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fpga_bytes = 0;
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fpga_bytes = 0;
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fpga_checksum = 0;
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fpga_checksum = 0;
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** post_fpga_config **********************************************
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***** post_fpga_config **********************************************
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********************************************************************* */
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********************************************************************* */
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static void post_fpga_config () {
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static void post_fpga_config () {
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POST_FPGA_CONFIG
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POST_FPGA_CONFIG
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** finish_fpga_configuration *************************************
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***** finish_fpga_configuration *************************************
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********************************************************************* */
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********************************************************************* */
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static void finish_fpga_configuration () {
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static void finish_fpga_configuration () {
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BYTE w;
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BYTE w;
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fpga_init_b += (IOE & bmBIT1) ? 22 : 11;
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fpga_init_b += (IOE & bmBIT1) ? 22 : 11;
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for ( w=0; w<64; w++ ) {
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for ( w=0; w<64; w++ ) {
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IOC6 = 1; IOC6 = 0;
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IOC6 = 1; IOC6 = 0;
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}
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}
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IOE |= bmBIT2; // CSI = 1
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IOE |= bmBIT2; // CSI = 1
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IOC6 = 1; IOC6 = 0;
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IOC6 = 1; IOC6 = 0;
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IOC6 = 1; IOC6 = 0;
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IOC6 = 1; IOC6 = 0;
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IOC6 = 1; IOC6 = 0;
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IOC6 = 1; IOC6 = 0;
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IOC6 = 1; IOC6 = 0;
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IOC6 = 1; IOC6 = 0;
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OEE = 0;
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OEE = 0;
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OEC = OOEC;
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OEC = OOEC;
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if ( IOE & bmBIT0 ) {
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if ( IOE & bmBIT0 ) {
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post_fpga_config();
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post_fpga_config();
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}
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}
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}
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}
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/* *********************************************************************
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/* *********************************************************************
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***** EP0 vendor request 0x30 ***************************************
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***** EP0 vendor request 0x30 ***************************************
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********************************************************************* */
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********************************************************************* */
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ADD_EP0_VENDOR_REQUEST((0x30,, // get FPGA state
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ADD_EP0_VENDOR_REQUEST((0x30,, // get FPGA state
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MEM_COPY1(fpga_checksum,EP0BUF+1,7);
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MEM_COPY1(fpga_checksum,EP0BUF+1,7);
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if ( IOE & bmBIT0 ) {
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if ( IOE & bmBIT0 ) {
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EP0BUF[0] = 0; // FPGA configured
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EP0BUF[0] = 0; // FPGA configured
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}
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}
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else {
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else {
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EP0BUF[0] = 1; // FPGA unconfigured
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EP0BUF[0] = 1; // FPGA unconfigured
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OEE = 0;
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OEE = 0;
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reset_fpga(); // prepare FPGA for configuration
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reset_fpga(); // prepare FPGA for configuration
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}
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}
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// EP0BUF[8] = 0; // bit order for bitstream in Flash memory: non-swapped
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// EP0BUF[8] = 0; // bit order for bitstream in Flash memory: non-swapped
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EP0BUF[8] = 1; // bit order for bitstream in Flash memory: swapped
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EP0BUF[8] = 1; // bit order for bitstream in Flash memory: swapped
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EP0BCH = 0;
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EP0BCH = 0;
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EP0BCL = 9;
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EP0BCL = 9;
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,,));;
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,,));;
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/* *********************************************************************
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/* *********************************************************************
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***** EP0 vendor command 0x31 ***************************************
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***** EP0 vendor command 0x31 ***************************************
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********************************************************************* */
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********************************************************************* */
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ADD_EP0_VENDOR_COMMAND((0x31,,reset_fpga();,,));; // reset FPGA
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ADD_EP0_VENDOR_COMMAND((0x31,,reset_fpga();,,));; // reset FPGA
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/* *********************************************************************
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/* *********************************************************************
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***** EP0 vendor command 0x32 ***************************************
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***** EP0 vendor command 0x32 ***************************************
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********************************************************************* */
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********************************************************************* */
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void fpga_send_ep0() { // send FPGA configuration data
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void fpga_send_ep0() { // send FPGA configuration data
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BYTE oOEB;
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BYTE oOEB;
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oOEB = OEB;
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oOEB = OEB;
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OEB = 255;
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OEB = 255;
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fpga_bytes += ep0_payload_transfer;
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fpga_bytes += ep0_payload_transfer;
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__asm
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__asm
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mov dptr,#_EP0BCL
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mov dptr,#_EP0BCL
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movx a,@dptr
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movx a,@dptr
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jz 010000$
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jz 010000$
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mov r2,a
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mov r2,a
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mov _AUTOPTRL1,#(_EP0BUF)
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mov _AUTOPTRL1,#(_EP0BUF)
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mov _AUTOPTRH1,#(_EP0BUF >> 8)
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mov _AUTOPTRH1,#(_EP0BUF >> 8)
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mov _AUTOPTRSETUP,#0x07
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mov _AUTOPTRSETUP,#0x07
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mov dptr,#_fpga_checksum
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mov dptr,#_fpga_checksum
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movx a,@dptr
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movx a,@dptr
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mov r1,a
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mov r1,a
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mov dptr,#_XAUTODAT1
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mov dptr,#_XAUTODAT1
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010001$:
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010001$:
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movx a,@dptr // 2
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movx a,@dptr // 2
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mov _IOB,a // 2
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mov _IOB,a // 2
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setb _IOC6 // 2
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setb _IOC6 // 2
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add a,r1 // 1
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add a,r1 // 1
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mov r1,a // 1
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mov r1,a // 1
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clr _IOC6 // 2
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clr _IOC6 // 2
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djnz r2, 010001$ // 4
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djnz r2, 010001$ // 4
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mov dptr,#_fpga_checksum
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mov dptr,#_fpga_checksum
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mov a,r1
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mov a,r1
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movx @dptr,a
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movx @dptr,a
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010000$:
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010000$:
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__endasm;
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__endasm;
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OEB = oOEB;
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OEB = oOEB;
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if ( EP0BCL<64 ) {
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if ( EP0BCL<64 ) {
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finish_fpga_configuration();
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finish_fpga_configuration();
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}
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}
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}
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}
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ADD_EP0_VENDOR_COMMAND((0x32,, // send FPGA configuration data
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ADD_EP0_VENDOR_COMMAND((0x32,, // send FPGA configuration data
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if ( fpga_conf_initialized != 123 )
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if ( fpga_conf_initialized != 123 )
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init_fpga_configuration();
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init_fpga_configuration();
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,,
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,,
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fpga_send_ep0();
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fpga_send_ep0();
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));;
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));;
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#ifdef[HS_FPGA_CONF_EP]
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#ifdef[HS_FPGA_CONF_EP]
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#ifeq[HS_FPGA_CONF_EP][2]
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#ifeq[HS_FPGA_CONF_EP][2]
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#elifeq[HS_FPGA_CONF_EP][4]
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#elifeq[HS_FPGA_CONF_EP][4]
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#elifeq[HS_FPGA_CONF_EP][6]
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#elifeq[HS_FPGA_CONF_EP][6]
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#elifneq[HS_FPGA_CONF_EP][8]
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#elifneq[HS_FPGA_CONF_EP][8]
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#error[`HS_FPGA_CONF_EP' is not defined correctly. Valid values are: `2', `4', `6', `8'.]
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#error[`HS_FPGA_CONF_EP' is not defined correctly. Valid values are: `2', `4', `6', `8'.]
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#endif
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#endif
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#define[@CAPABILITY_HS_FPGA;]
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#define[@CAPABILITY_HS_FPGA;]
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/* *********************************************************************
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/* *********************************************************************
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***** EP0 vendor request 0x33 ***************************************
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***** EP0 vendor request 0x33 ***************************************
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********************************************************************* */
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********************************************************************* */
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ADD_EP0_VENDOR_REQUEST((0x33,, // get high speed fpga configuration endpoint and interface
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ADD_EP0_VENDOR_REQUEST((0x33,, // get high speed fpga configuration endpoint and interface
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EP0BUF[0] = HS_FPGA_CONF_EP; // endpoint
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EP0BUF[0] = HS_FPGA_CONF_EP; // endpoint
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EP0BUF[1] = EPHS_FPGA_CONF_EP_INTERFACE; // interface
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EP0BUF[1] = EPHS_FPGA_CONF_EP_INTERFACE; // interface
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EP0BCH = 0;
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EP0BCH = 0;
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EP0BCL = 2;
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EP0BCL = 2;
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,,));;
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,,));;
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/* *********************************************************************
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/* *********************************************************************
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***** EP0 vendor command 0x34 ***************************************
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***** EP0 vendor command 0x34 ***************************************
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********************************************************************* */
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********************************************************************* */
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// FIFO write wave form
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// FIFO write wave form
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const char __xdata GPIF_WAVE_DATA_HSFPGA_24MHZ[32] =
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const char __xdata GPIF_WAVE_DATA_HSFPGA_24MHZ[32] =
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{
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{
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/* LenBr */ 0x01, 0x88, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
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/* LenBr */ 0x01, 0x88, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
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/* Opcode*/ 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
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/* Opcode*/ 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
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/* Output*/ 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
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/* Output*/ 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
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/* LFun */ 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
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/* LFun */ 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
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};
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};
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const char __xdata GPIF_WAVE_DATA_HSFPGA_12MHZ[32] =
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const char __xdata GPIF_WAVE_DATA_HSFPGA_12MHZ[32] =
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{
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{
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/* LenBr */ 0x02, 0x01, 0x90, 0x01, 0x01, 0x01, 0x01, 0x07,
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/* LenBr */ 0x02, 0x01, 0x90, 0x01, 0x01, 0x01, 0x01, 0x07,
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/* Opcode*/ 0x02, 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x00,
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/* Opcode*/ 0x02, 0x02, 0x07, 0x02, 0x02, 0x02, 0x02, 0x00,
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/* Output*/ 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
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/* Output*/ 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
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/* LFun */ 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x3F,
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/* LFun */ 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x3F,
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};
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};
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void init_cpld_fpga_configuration() {
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void init_cpld_fpga_configuration() {
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IFCONFIG = bmBIT7 | bmBIT6 | 2; // Internal source, 48MHz, GPIF
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IFCONFIG = bmBIT7 | bmBIT6 | 2; // Internal source, 48MHz, GPIF
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|
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GPIFREADYCFG = 0;
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GPIFREADYCFG = 0;
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GPIFCTLCFG = 0x0;
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GPIFCTLCFG = 0x0;
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GPIFIDLECS = 0;
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GPIFIDLECS = 0;
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GPIFIDLECTL = 4;
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GPIFIDLECTL = 4;
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GPIFWFSELECT = 0x4E;
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GPIFWFSELECT = 0x4E;
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GPIFREADYSTAT = 0;
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GPIFREADYSTAT = 0;
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|
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MEM_COPY1(GPIF_WAVE_DATA_HSFPGA_24MHZ,GPIF_WAVE3_DATA,32);
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MEM_COPY1(GPIF_WAVE_DATA_HSFPGA_24MHZ,GPIF_WAVE3_DATA,32);
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|
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FLOWSTATE = 0;
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FLOWSTATE = 0;
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FLOWLOGIC = 0x10;
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FLOWLOGIC = 0x10;
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FLOWEQ0CTL = 0;
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FLOWEQ0CTL = 0;
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FLOWEQ1CTL = 0;
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FLOWEQ1CTL = 0;
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FLOWHOLDOFF = 0;
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FLOWHOLDOFF = 0;
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FLOWSTB = 0;
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FLOWSTB = 0;
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FLOWSTBEDGE = 0;
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FLOWSTBEDGE = 0;
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FLOWSTBHPERIOD = 0;
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FLOWSTBHPERIOD = 0;
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|
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REVCTL = 0x1; // reset fifo
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REVCTL = 0x1; // reset fifo
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SYNCDELAY;
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SYNCDELAY;
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FIFORESET = 0x80;
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FIFORESET = 0x80;
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SYNCDELAY;
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SYNCDELAY;
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FIFORESET = HS_FPGA_CONF_EP;
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FIFORESET = HS_FPGA_CONF_EP;
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SYNCDELAY;
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SYNCDELAY;
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FIFORESET = 0x0;
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FIFORESET = 0x0;
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SYNCDELAY;
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SYNCDELAY;
|
|
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EPHS_FPGA_CONF_EPFIFOCFG = 0; // config fifo
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EPHS_FPGA_CONF_EPFIFOCFG = 0; // config fifo
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SYNCDELAY;
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SYNCDELAY;
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EPHS_FPGA_CONF_EPFIFOCFG = bmBIT4 | 0;
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EPHS_FPGA_CONF_EPFIFOCFG = bmBIT4 | 0;
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SYNCDELAY;
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SYNCDELAY;
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EPHS_FPGA_CONF_EPGPIFFLGSEL = 1;
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EPHS_FPGA_CONF_EPGPIFFLGSEL = 1;
|
SYNCDELAY;
|
SYNCDELAY;
|
|
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GPIFTCB3 = 1; // abort after at least 14*65536 transactions
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GPIFTCB3 = 1; // abort after at least 14*65536 transactions
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SYNCDELAY;
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SYNCDELAY;
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GPIFTCB2 = 0;
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GPIFTCB2 = 0;
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SYNCDELAY;
|
SYNCDELAY;
|
GPIFTCB1 = 0;
|
GPIFTCB1 = 0;
|
SYNCDELAY;
|
SYNCDELAY;
|
GPIFTCB0 = 0;
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GPIFTCB0 = 0;
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SYNCDELAY;
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SYNCDELAY;
|
|
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EPHS_FPGA_CONF_EPGPIFTRIG = 0xff; // arm fifos
|
EPHS_FPGA_CONF_EPGPIFTRIG = 0xff; // arm fifos
|
SYNCDELAY;
|
SYNCDELAY;
|
|
|
OEC &= ~bmBIT6; // disable CCLK output
|
OEC &= ~bmBIT6; // disable CCLK output
|
IOE = bmBIT4 | bmBIT7; // HS config mode
|
IOE = bmBIT4 | bmBIT7; // HS config mode
|
}
|
}
|
|
|
|
|
ADD_EP0_VENDOR_COMMAND((0x34,, // init fpga configuration
|
ADD_EP0_VENDOR_COMMAND((0x34,, // init fpga configuration
|
init_fpga_configuration();
|
init_fpga_configuration();
|
|
|
EPHS_FPGA_CONF_EPCS &= ~bmBIT0; // clear stall bit
|
EPHS_FPGA_CONF_EPCS &= ~bmBIT0; // clear stall bit
|
|
|
GPIFABORT = 0xFF; // abort pendig
|
GPIFABORT = 0xFF; // abort pendig
|
|
|
init_cpld_fpga_configuration();
|
init_cpld_fpga_configuration();
|
|
|
,,));;
|
,,));;
|
|
|
|
|
/* *********************************************************************
|
/* *********************************************************************
|
***** EP0 vendor command 0x35 ***************************************
|
***** EP0 vendor command 0x35 ***************************************
|
********************************************************************* */
|
********************************************************************* */
|
ADD_EP0_VENDOR_COMMAND((0x35,, // finish fpga configuration
|
ADD_EP0_VENDOR_COMMAND((0x35,, // finish fpga configuration
|
IOE = bmBIT3 | bmBIT7;
|
IOE = bmBIT3 | bmBIT7;
|
OEC |= bmBIT6; // out: CCLK
|
OEC |= bmBIT6; // out: CCLK
|
|
|
GPIFABORT = 0xFF;
|
GPIFABORT = 0xFF;
|
SYNCDELAY;
|
SYNCDELAY;
|
IFCONFIG &= 0xf0;
|
IFCONFIG &= 0xf0;
|
SYNCDELAY;
|
SYNCDELAY;
|
|
|
finish_fpga_configuration();
|
finish_fpga_configuration();
|
,,));;
|
,,));;
|
|
|
#endif // HS_FPGA_CONF_EP
|
#endif // HS_FPGA_CONF_EP
|
|
|
#ifeq[FLASH_BITSTREAM_ENABLED][1]
|
#ifeq[FLASH_BITSTREAM_ENABLED][1]
|
/* *********************************************************************
|
/* *********************************************************************
|
***** fpga_configure_from_flash *************************************
|
***** fpga_configure_from_flash *************************************
|
********************************************************************* */
|
********************************************************************* */
|
/*
|
/*
|
Configure the FPGA using a bitstream from flash.
|
Configure the FPGA using a bitstream from flash.
|
If force == 0 a already configured FPGA is not re-configured.
|
If force == 0 a already configured FPGA is not re-configured.
|
Return values:
|
Return values:
|
0 : Configuration successful
|
0 : Configuration successful
|
1 : FPGA already configured
|
1 : FPGA already configured
|
4 : Configuration error
|
4 : Configuration error
|
*/
|
*/
|
#define[SPI_CS][IOSPI_PORTSPI_BIT_CS]
|
#define[SPI_CS][IOSPI_PORTSPI_BIT_CS]
|
#define[SPI_PORT][C]
|
#define[SPI_PORT][C]
|
#define[SPI_BIT_DO][4]
|
#define[SPI_BIT_DO][4]
|
#define[SPI_BIT_CS][5]
|
#define[SPI_BIT_CS][5]
|
#define[SPI_BIT_CLK][6]
|
#define[SPI_BIT_CLK][6]
|
#define[SPI_BIT_DI][7]
|
#define[SPI_BIT_DI][7]
|
|
|
BYTE fpga_configure_from_flash( BYTE force) {
|
BYTE fpga_configure_from_flash( BYTE force) {
|
BYTE c;
|
BYTE c;
|
WORD i;
|
WORD i;
|
|
|
if ( ( force == 0 ) && ( IOE & bmBIT0 ) ) {
|
if ( ( force == 0 ) && ( IOE & bmBIT0 ) ) {
|
fpga_flash_result = 1;
|
fpga_flash_result = 1;
|
return 1;
|
return 1;
|
}
|
}
|
|
|
fpga_flash_result = 0;
|
fpga_flash_result = 0;
|
|
|
c = OESPI_PORT;
|
c = OESPI_PORT;
|
OESPI_PORT &= ~( bmBITSPI_BIT_CS | bmBITSPI_BIT_DI | bmBITSPI_BIT_CLK ); // disable SPI outputs
|
OESPI_PORT &= ~( bmBITSPI_BIT_CS | bmBITSPI_BIT_DI | bmBITSPI_BIT_CLK ); // disable SPI outputs
|
|
|
{
|
{
|
PRE_FPGA_RESET
|
PRE_FPGA_RESET
|
}
|
}
|
|
|
// reset FPGA and start configuration from flash
|
// reset FPGA and start configuration from flash
|
// out: CM0 CM1 RESET_N CSI RDWR
|
// out: CM0 CM1 RESET_N CSI RDWR
|
OEE = bmBIT3 | bmBIT4 | bmBIT7;
|
OEE = bmBIT3 | bmBIT4 | bmBIT7;
|
IOE = 0;
|
IOE = 0;
|
wait(1);
|
wait(1);
|
IOE = bmBIT7;
|
IOE = bmBIT7;
|
|
|
// wait up to 10s for CS going high
|
// wait up to 10s for CS going high
|
wait(10);
|
wait(10);
|
for (i=0; (IOE & bmBIT1) && (SPI_CS==0) && i<10000; i++ ) {
|
for (i=0; (IOE & bmBIT1) && (SPI_CS==0) && i<10000; i++ ) {
|
wait(1);
|
wait(1);
|
}
|
}
|
|
|
wait(1);
|
wait(1);
|
|
|
if ( IOE & bmBIT0 ) {
|
if ( IOE & bmBIT0 ) {
|
post_fpga_config();
|
post_fpga_config();
|
}
|
}
|
else {
|
else {
|
IOE = bmBIT3 | bmBIT4; // leave master SPI config mode
|
IOE = bmBIT3 | bmBIT4; // leave master SPI config mode
|
wait(1);
|
wait(1);
|
fpga_flash_result = 4;
|
fpga_flash_result = 4;
|
}
|
}
|
OEE = 0;
|
OEE = 0;
|
|
|
OESPI_PORT = c;
|
OESPI_PORT = c;
|
SPI_CS = 1;
|
SPI_CS = 1;
|
|
|
return fpga_flash_result;
|
return fpga_flash_result;
|
}
|
}
|
|
|
#include[ztex-fpga-flash2.h]
|
#include[ztex-fpga-flash2.h]
|
|
|
#endif
|
#endif
|
|
|
|
|
#endif /*ZTEX_FPGA_H*/
|
#endif /*ZTEX_FPGA_H*/
|
|
|
