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/*
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/*!
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* Если error срабатывает на последнем байте пакета, то он не будет отправлен, пока
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* \brief UsB FT232H core module
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* не придет следующий пакет
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* \version 1.8
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*/
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*/
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module usb_ft232h (
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module usb_ft232h (
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//Avalon-MM Slave
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clk_i,
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clk_i,
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reset_i,
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reset_i,
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//Avalon-MM Slave
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address_i,
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address_i,
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read_i,
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read_i,
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readdata_o,
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readdata_o,
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readdatavalid_o,
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write_i,
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write_i,
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writedata_i,
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writedata_i,
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waitrequest_o,
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//FT232H
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//FT232H
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usb_clk_i,
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usb_clk_i,
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usb_data_io,
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usb_data_io,
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usb_rxf_n_i,
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usb_rxf_n_i,
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| Line 22... |
Line 25... |
usb_rd_n_o,
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usb_rd_n_o,
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usb_wr_n_o,
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usb_wr_n_o,
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usb_oe_n_o
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usb_oe_n_o
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);
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);
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parameter TX_FIFO_DEPTH = 512;
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parameter TX_FIFO_NUMWORDS = 512;
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parameter TX_FIFO_WIDTHU = 9;
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parameter TX_FIFO_WIDTHU = 9;
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parameter RX_FIFO_DEPTH = 512;
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parameter RX_FIFO_NUMWORDS = 512;
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parameter RX_FIFO_WIDTHU = 9;
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parameter RX_FIFO_WIDTHU = 9;
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parameter FIFOS_DELAYPIPE = 11;
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parameter USB_READ_LATENCY = 1;
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parameter USB_WRITE_LATENCY = 1;
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parameter AVALON_CMD_LATENCY = 1;
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parameter AVALON_READ_LATENCY = 1;
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parameter AVALON_WRITE_LATENCY = 1;
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localparam WRDATA_ADDR = 4'd0;
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localparam RDDATA_ADDR = 4'd1;
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localparam TXSTATUSL_ADDR = 4'd2;
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localparam TXSTATUSH_ADDR = 4'd3;
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localparam RXSTATUSL_ADDR = 4'd4;
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localparam RXSTATUSH_ADDR = 4'd5;
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input logic clk_i;
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input logic clk_i;
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input logic reset_i;
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input logic reset_i;
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input logic [3:0] address_i;
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input logic [2:0] address_i;
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input logic read_i;
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input logic read_i;
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output logic [7:0] readdata_o;
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output logic [7:0] readdata_o;
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output logic readdatavalid_o;
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input logic write_i;
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input logic write_i;
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input logic [7:0] writedata_i;
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input logic [7:0] writedata_i;
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output logic waitrequest_o;
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input logic usb_clk_i;
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input logic usb_clk_i;
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inout logic [7:0] usb_data_io;
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inout wire [7:0] usb_data_io;
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input logic usb_rxf_n_i;
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input logic usb_rxf_n_i;
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input logic usb_txe_n_i;
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input logic usb_txe_n_i;
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output logic usb_rd_n_o;
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output logic usb_rd_n_o;
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output logic usb_wr_n_o;
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output logic usb_wr_n_o;
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output logic usb_oe_n_o;
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output logic usb_oe_n_o;
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reg error;
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reg rxerror;
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reg [7:0] rxerrdata;
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logic [15:0] txstatus;
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logic [15:0] rxstatus;
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reg read_pipe;
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reg read_pipe2;
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reg adr_data;
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reg adr_txsl;
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reg adr_txsh;
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reg adr_rxsl;
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reg adr_rxsh;
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logic [7:0] txf_wrdata;
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logic [7:0] txf_wrdata;
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logic txf_wrclk;
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logic txf_wrclk;
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logic txf_wrreq;
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logic txf_wrreq;
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logic txf_wrfull;
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logic txf_wrfull;
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logic [TX_FIFO_WIDTHU-1:0] txf_wrusedw;
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logic [TX_FIFO_WIDTHU-1:0] txf_wrusedw;
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logic txf_rdclk;
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logic txf_rdclk;
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logic txf_rdreq;
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logic txf_rdreq;
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logic [7:0] txf_rddata;
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logic [7:0] txf_rddata;
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logic txf_rdempty;
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logic txf_rdempty;
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logic [7:0] rxf_wrdata;
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logic [7:0] rxf_wrdata;
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logic rxf_wrclk;
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logic rxf_wrclk;
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logic rxf_wrreq;
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logic rxf_wrreq;
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logic rxf_wrfull;
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logic rxf_wrfull;
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logic [RX_FIFO_WIDTHU-1:0] rxf_rdusedw;
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logic [RX_FIFO_WIDTHU-1:0] rxf_rdusedw;
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logic rxf_rdclk;
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logic rxf_rdclk;
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logic rxf_rdreq;
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logic rxf_rdreq;
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logic [7:0] rxf_rddata;
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logic [7:0] rxf_rddata;
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logic rxf_rdempty;
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logic rxf_rdempty;
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logic rxf_rdfull;
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logic rxf_rdfull;
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assign usb_data_io = ( usb_oe_n_o ) ? ( txf_rddata ) : ( {8{1'bZ}} );
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assign rxf_wrclk = ~usb_clk_i;
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assign txf_rdclk = usb_clk_i;
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ft232h_fifos_interface ffi (
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assign rxf_rdclk = clk_i;
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.reset_i (reset_i),
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assign txf_wrclk = ~clk_i;
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// FT232H
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.usb_clk_i (usb_clk_i),
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assign txstatus[15] = ~txf_wrfull; //can write
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.usb_data_io (usb_data_io),
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assign txstatus[14:TX_FIFO_WIDTHU+1] = 0;
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.usb_rxf_n_i (usb_rxf_n_i),
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assign txstatus[TX_FIFO_WIDTHU] = txf_wrfull;
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.usb_txe_n_i (usb_txe_n_i),
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assign txstatus[TX_FIFO_WIDTHU-1:0] = ( txf_wrfull ? {TX_FIFO_WIDTHU{1'b0}} : txf_wrusedw );
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.usb_rd_n_o (usb_rd_n_o),
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.usb_wr_n_o (usb_wr_n_o),
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assign rxstatus[15] = ~rxf_rdempty; //can read
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.usb_oe_n_o (usb_oe_n_o),
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assign rxstatus[14:RX_FIFO_WIDTHU+1] = 0;
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// RX FIFO
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assign rxstatus[RX_FIFO_WIDTHU] = rxf_rdfull;
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.rxf_wrclk_o (rxf_wrclk),
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assign rxstatus[RX_FIFO_WIDTHU-1:0] = ( rxf_rdempty ? {RX_FIFO_WIDTHU{1'b0}} : rxf_rdusedw );
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.rxf_wrfull_i (rxf_wrfull),
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.rxf_wrreq_o (rxf_wrreq),
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.rxf_wrdata_o (rxf_wrdata),
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// TX FIFO
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.txf_rdclk_o (txf_rdclk),
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.txf_rdempty_i (txf_rdempty),
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.txf_rdreq_o (txf_rdreq),
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.txf_rddata_i (txf_rddata)
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);
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defparam
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ffi.READ_LATENCY = USB_READ_LATENCY,
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ffi.WRITE_LATENCY = USB_WRITE_LATENCY;
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dcfifo txfifo (
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dcfifo txfifo (
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.aclr ( reset_i ),
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.aclr ( reset_i ),
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.data ( txf_wrdata ),
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.data ( txf_wrdata ),
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| Line 126... |
Line 131... |
.rdfull (),
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.rdfull (),
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.rdusedw (),
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.rdusedw (),
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.wrempty ());
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.wrempty ());
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defparam
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defparam
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txfifo.intended_device_family = "Cyclone IV E",
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txfifo.intended_device_family = "Cyclone IV E",
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txfifo.lpm_numwords = TX_FIFO_DEPTH,
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txfifo.lpm_numwords = TX_FIFO_NUMWORDS,
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txfifo.lpm_showahead = "OFF",
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txfifo.lpm_showahead = "OFF",
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txfifo.lpm_type = "dcfifo",
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txfifo.lpm_type = "dcfifo",
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txfifo.lpm_width = 8,
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txfifo.lpm_width = 8,
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txfifo.lpm_widthu = TX_FIFO_WIDTHU,
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txfifo.lpm_widthu = TX_FIFO_WIDTHU,
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txfifo.overflow_checking = "ON",
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txfifo.overflow_checking = "ON",
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txfifo.rdsync_delaypipe = 11,
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txfifo.rdsync_delaypipe = FIFOS_DELAYPIPE,
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txfifo.read_aclr_synch = "ON",
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txfifo.read_aclr_synch = "ON",
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txfifo.underflow_checking = "ON",
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txfifo.underflow_checking = "ON",
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txfifo.use_eab = "ON",
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txfifo.use_eab = "ON",
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txfifo.write_aclr_synch = "ON",
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txfifo.write_aclr_synch = "ON",
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txfifo.wrsync_delaypipe = 11;
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txfifo.wrsync_delaypipe = FIFOS_DELAYPIPE;
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dcfifo rxfifo (
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dcfifo rxfifo (
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.aclr ( reset_i ),
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.aclr ( reset_i ),
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.data ( rxf_wrdata ),
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.data ( rxf_wrdata ),
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| Line 157... |
Line 162... |
.rdfull ( rxf_rdfull ),
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.rdfull ( rxf_rdfull ),
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.rdusedw ( rxf_rdusedw ),
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.rdusedw ( rxf_rdusedw ),
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.wrempty ());
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.wrempty ());
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defparam
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defparam
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rxfifo.intended_device_family = "Cyclone IV E",
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rxfifo.intended_device_family = "Cyclone IV E",
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rxfifo.lpm_numwords = RX_FIFO_DEPTH,
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rxfifo.lpm_numwords = RX_FIFO_NUMWORDS,
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rxfifo.lpm_showahead = "OFF",
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rxfifo.lpm_showahead = "OFF",
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rxfifo.lpm_type = "dcfifo",
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rxfifo.lpm_type = "dcfifo",
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rxfifo.lpm_width = 8,
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rxfifo.lpm_width = 8,
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rxfifo.lpm_widthu = RX_FIFO_WIDTHU,
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rxfifo.lpm_widthu = RX_FIFO_WIDTHU,
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rxfifo.overflow_checking = "ON",
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rxfifo.overflow_checking = "ON",
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rxfifo.rdsync_delaypipe = 11,
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rxfifo.rdsync_delaypipe = FIFOS_DELAYPIPE,
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rxfifo.read_aclr_synch = "ON",
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rxfifo.read_aclr_synch = "ON",
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rxfifo.underflow_checking = "ON",
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rxfifo.underflow_checking = "ON",
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rxfifo.use_eab = "ON",
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rxfifo.use_eab = "ON",
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rxfifo.write_aclr_synch = "ON",
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rxfifo.write_aclr_synch = "ON",
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rxfifo.wrsync_delaypipe = 11;
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rxfifo.wrsync_delaypipe = FIFOS_DELAYPIPE;
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/* read usb data to rx fifo */
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usb_fifos_avalon_mm_interface ufai (
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always_ff @( negedge rxf_wrclk or posedge reset_i )
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.reset_i (reset_i),
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begin
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.clk_i (clk_i),
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if( reset_i )
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// Avalon-MM
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begin
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.address_i (address_i),
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rxf_wrreq <= 1'b0;
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.read_i (read_i),
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rxf_wrdata <= 8'b0;
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.readdata_o (readdata_o),
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rxerror <= 1'b0;
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.readdatavalid_o (readdatavalid_o),
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rxerrdata <= 8'b0;
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.write_i (write_i),
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end
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.writedata_i (writedata_i),
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else
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.waitrequest_o (waitrequest_o),
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begin
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// RX FIFO
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if( ~usb_rd_n_o & rxf_wrfull )
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.rxf_rdclk_o (rxf_rdclk),
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begin
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.rxf_rdempty_i (rxf_rdempty),
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rxerror <= 1'b1;
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.rxf_rdfull_i (rxf_rdfull),
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rxerrdata <= usb_data_io;
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.rxf_rdreq_o (rxf_rdreq),
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end
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.rxf_rddata_i (rxf_rddata),
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.rxf_rdusedw_i (rxf_rdusedw),
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if( ~rxf_wrfull & ((~usb_rd_n_o & ~usb_rxf_n_i) | rxerror) )
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// TX FIFO
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begin
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.txf_wrclk_o (txf_wrclk),
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rxf_wrreq <= 1'b1;
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.txf_wrfull_i (txf_wrfull),
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if( rxerror )
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.txf_wrreq_o (txf_wrreq),
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begin
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.txf_wrdata_o (txf_wrdata),
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rxerror <= 1'b0;
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.txf_wrusedw_i (txf_wrusedw)
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rxf_wrdata <= rxerrdata;
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);
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end
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defparam
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else
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ufai.TX_FIFO_WIDTHU = TX_FIFO_WIDTHU,
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rxf_wrdata <= usb_data_io;
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ufai.RX_FIFO_WIDTHU = RX_FIFO_WIDTHU,
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end
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ufai.CMD_LATENCY = AVALON_CMD_LATENCY,
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else
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ufai.READ_LATENCY = AVALON_READ_LATENCY,
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begin
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ufai.WRITE_LATENCY = AVALON_WRITE_LATENCY;
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rxf_wrreq <= 1'b0;
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end
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end
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end
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always_ff @( posedge usb_clk_i or posedge reset_i )
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begin
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if( reset_i )
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begin
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usb_oe_n_o <= 1'b1;
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usb_rd_n_o <= 1'b1;
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end
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else
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begin
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if( ~usb_rxf_n_i & ~rxf_wrfull & ( usb_txe_n_i | ( ~txf_rdreq & ~error )) & ~rxerror )
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begin
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usb_oe_n_o <= 1'b0;
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if( ~usb_oe_n_o )
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usb_rd_n_o <= 1'b0;
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end
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else
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begin
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usb_oe_n_o <= 1'b1;
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usb_rd_n_o <= 1'b1;
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end
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end
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end
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/*---------------------------------*/
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/* write tx fifo data to usb */
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always_ff @( negedge txf_rdclk or posedge reset_i )
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begin
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if( reset_i )
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begin
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txf_rdreq <= 1'b0;
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end
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else
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begin
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if( ~usb_txe_n_i & ~txf_rdempty & ~error & usb_oe_n_o )
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begin
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txf_rdreq <= 1'b1;
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end
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else
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txf_rdreq <= 1'b0;
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end
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end
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always_ff @( posedge usb_clk_i or posedge reset_i )
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begin
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if( reset_i )
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begin
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usb_wr_n_o <= 1'b1;
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error <= 1'b0;
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end
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else
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begin
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if( usb_txe_n_i & ~usb_wr_n_o )
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begin
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error <= 1'b1;
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end
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if( ~usb_txe_n_i & ( txf_rdreq | error ) & usb_oe_n_o )
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begin
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usb_wr_n_o <= 1'b0;
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if( error )
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error <= 1'b0;
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end
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else
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begin
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usb_wr_n_o <= 1'b1;
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end
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end
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end
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/*-----------------------------*/
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/* avalon data to tx fifo*/
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always_ff @( negedge txf_wrclk or posedge reset_i )
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begin
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if( reset_i )
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begin
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txf_wrreq <= 1'b0;
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txf_wrdata <= 8'b0;
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end
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else
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begin
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if( write_i & ( address_i == WRDATA_ADDR ) & ~txf_wrfull )
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begin
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txf_wrreq <= 1'b1;
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txf_wrdata <= writedata_i;
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end
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else
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begin
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txf_wrreq <= 1'b0;
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end
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end
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end
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/*------------------------------------*/
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/* rx fifo data to avalon */
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always_ff @( posedge clk_i or posedge reset_i )
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begin
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if( reset_i )
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begin
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adr_data <= 1'b0;
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adr_txsl <= 1'b0;
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adr_txsh <= 1'b0;
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adr_rxsl <= 1'b0;
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adr_rxsh <= 1'b0;
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end
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else
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begin
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if( read_i )
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begin
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if( address_i == RDDATA_ADDR )
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adr_data <= 1'b1;
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else
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adr_data <= 1'b0;
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if( address_i == TXSTATUSL_ADDR )
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adr_txsl <= 1'b1;
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else
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adr_txsl <= 1'b0;
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if( address_i == TXSTATUSH_ADDR )
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adr_txsh <= 1'b1;
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else
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adr_txsh <= 1'b0;
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if( address_i == RXSTATUSL_ADDR )
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adr_rxsl <= 1'b1;
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else
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adr_rxsl <= 1'b0;
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if( address_i == RXSTATUSH_ADDR )
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adr_rxsh <= 1'b1;
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else
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adr_rxsh <= 1'b0;
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end
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end
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end
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always_ff @( posedge clk_i or posedge reset_i )
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begin
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if( reset_i )
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begin
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read_pipe <= 1'b0;
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end
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else
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begin
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if( read_i )
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read_pipe <= 1'b1;
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else
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read_pipe <= 1'b0;
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end
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end
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always_ff @( negedge rxf_rdclk or posedge reset_i )
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begin
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if( reset_i )
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begin
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rxf_rdreq <= 1'b0;
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end
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else
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begin
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if( read_pipe & adr_data & ~rxf_rdempty )
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rxf_rdreq <= 1'b1;
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else
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rxf_rdreq <= 1'b0;
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end
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end
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always_ff @( posedge clk_i or posedge reset_i )
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begin
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if( reset_i )
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begin
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read_pipe2 <= 1'b0;
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end
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else
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begin
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if( read_pipe )
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read_pipe2 <= 1'b1;
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else
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read_pipe2 <= 1'b0;
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end
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end
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always_ff @( posedge clk_i or posedge reset_i )
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begin
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if( reset_i )
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begin
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readdata_o <= 8'b0;
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end
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else
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begin
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if( read_pipe2 )
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begin
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if( adr_data )
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readdata_o <= rxf_rddata;
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else if( adr_txsl )
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readdata_o <= txstatus[7:0];
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else if( adr_txsh )
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readdata_o <= txstatus[15:8];
|
|
else if( adr_rxsl )
|
|
readdata_o <= rxstatus[7:0];
|
|
else if( adr_rxsh )
|
|
readdata_o <= rxstatus[15:8];
|
|
else
|
|
readdata_o <= 8'b0;
|
|
end
|
|
end
|
|
end
|
|
/*------------------------------------*/
|
|
|
|
|
|
endmodule
|
endmodule
|
