| Line 18... |
Line 18... |
programming logic devices manufactured by Altera and sold by
|
programming logic devices manufactured by Altera and sold by
|
Altera or its authorized distributors. Please refer to the
|
Altera or its authorized distributors. Please refer to the
|
applicable agreement for further details.
|
applicable agreement for further details.
|
*/
|
*/
|
|
|
VECTOR("C:/Altera/qdesigns/usimplez/db/usimplez.sim.cvwf")
|
VECTOR("C:/Altera/qdesigns/usimplez00/usimplez_top.vwf")
|
{
|
{
|
ZOOM{
|
ZOOM{
|
ZBEGIN = 0;
|
ZBEGIN = 0;
|
ZEND = 1723586;
|
ZEND = 100800;
|
NUMERATOR = 542;
|
NUMERATOR = 504;
|
DENOMINATOR = 1723586;
|
DENOMINATOR = 100800;
|
TOP_INDEX = 0;
|
TOP_INDEX = 0;
|
}
|
}
|
CLOCK{
|
CLOCK{
|
PERIOD = 10000;
|
PERIOD = 50000;
|
OFFSET = 0;
|
OFFSET = 0;
|
DUTY_CYCLE = 50;
|
DUTY_CYCLE = 50;
|
}
|
}
|
RANDOM_VALUE{
|
RANDOM_VALUE{
|
INTERVAL_TYPE = HALF_GRID;
|
INTERVAL_TYPE = HALF_GRID;
|
| Line 52... |
Line 52... |
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "we_o";
|
SIGNAL = "in0_o";
|
INDEX = 2;
|
INDEX = 2;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "in0_o";
|
SIGNAL = "in1_o";
|
INDEX = 3;
|
INDEX = 3;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "in1_o";
|
SIGNAL = "op0_o";
|
INDEX = 4;
|
INDEX = 4;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "op0_o";
|
SIGNAL = "op1_o";
|
INDEX = 5;
|
INDEX = 5;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "op1_o";
|
SIGNAL = "we_o";
|
INDEX = 6;
|
INDEX = 6;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s";
|
INDEX = 7;
|
INDEX = 7;
|
FORMAT = T;
|
FORMAT = T;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[11]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[11]";
|
INDEX = 8;
|
INDEX = 8;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[10]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[10]";
|
INDEX = 9;
|
INDEX = 9;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[9]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[9]";
|
INDEX = 10;
|
INDEX = 10;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[8]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[8]";
|
INDEX = 11;
|
INDEX = 11;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[7]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[7]";
|
INDEX = 12;
|
INDEX = 12;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[6]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[6]";
|
INDEX = 13;
|
INDEX = 13;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[5]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[5]";
|
INDEX = 14;
|
INDEX = 14;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[4]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[4]";
|
INDEX = 15;
|
INDEX = 15;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[3]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[3]";
|
INDEX = 16;
|
INDEX = 16;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[2]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[2]";
|
INDEX = 17;
|
INDEX = 17;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[1]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[1]";
|
INDEX = 18;
|
INDEX = 18;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[0]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[0]";
|
INDEX = 19;
|
INDEX = 19;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
| Line 573... |
Line 573... |
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
}
|
}
|
|
|
VECTOR("C:/Altera/qdesigns/usimplez/usimplez_top.vwf")
|
VECTOR("C:/Altera/qdesigns/usimplez00/db/usimplez_top.sim.cvwf")
|
{
|
{
|
ZOOM{
|
ZOOM{
|
ZBEGIN = 0;
|
ZBEGIN = 0;
|
ZEND = 269600;
|
ZEND = 1345651;
|
NUMERATOR = 674;
|
NUMERATOR = 428;
|
DENOMINATOR = 269600;
|
DENOMINATOR = 930434;
|
TOP_INDEX = 0;
|
TOP_INDEX = 0;
|
}
|
}
|
CLOCK{
|
CLOCK{
|
PERIOD = 50000;
|
PERIOD = 10000;
|
OFFSET = 0;
|
OFFSET = 0;
|
DUTY_CYCLE = 50;
|
DUTY_CYCLE = 50;
|
}
|
}
|
RANDOM_VALUE{
|
RANDOM_VALUE{
|
INTERVAL_TYPE = HALF_GRID;
|
INTERVAL_TYPE = HALF_GRID;
|
| Line 607... |
Line 607... |
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "we_o";
|
SIGNAL = "in0_o";
|
INDEX = 2;
|
INDEX = 2;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "in0_o";
|
SIGNAL = "in1_o";
|
INDEX = 3;
|
INDEX = 3;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "in1_o";
|
SIGNAL = "op0_o";
|
INDEX = 4;
|
INDEX = 4;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "op0_o";
|
SIGNAL = "op1_o";
|
INDEX = 5;
|
INDEX = 5;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "op1_o";
|
SIGNAL = "we_o";
|
INDEX = 6;
|
INDEX = 6;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s";
|
INDEX = 7;
|
INDEX = 7;
|
FORMAT = T;
|
FORMAT = T;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[11]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[11]";
|
INDEX = 8;
|
INDEX = 8;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[10]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[10]";
|
INDEX = 9;
|
INDEX = 9;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[9]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[9]";
|
INDEX = 10;
|
INDEX = 10;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[8]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[8]";
|
INDEX = 11;
|
INDEX = 11;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[7]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[7]";
|
INDEX = 12;
|
INDEX = 12;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[6]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[6]";
|
INDEX = 13;
|
INDEX = 13;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[5]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[5]";
|
INDEX = 14;
|
INDEX = 14;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[4]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[4]";
|
INDEX = 15;
|
INDEX = 15;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[3]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[3]";
|
INDEX = 16;
|
INDEX = 16;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[2]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[2]";
|
INDEX = 17;
|
INDEX = 17;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[1]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[1]";
|
INDEX = 18;
|
INDEX = 18;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
}
|
}
|
LINE{
|
LINE{
|
SIGNAL = "usimplez_cpu:cpu|acumulador[0]";
|
SIGNAL = "usimplez_cpu:cpu|ac_reg_s[0]";
|
INDEX = 19;
|
INDEX = 19;
|
FORMAT = E;
|
FORMAT = E;
|
SCALE = 1;
|
SCALE = 1;
|
VISIBLE = Y;
|
VISIBLE = Y;
|
FLAG = N;
|
FLAG = N;
|
