URL
https://opencores.org/ocsvn/verilog_fixed_point_math_library/verilog_fixed_point_math_library/trunk
Show entire file |
Details |
Blame |
View Log
| Rev 4 |
Rev 7 |
| Line 35... |
Line 35... |
|
|
reg [2*N-2:0] reg_working_result; // a place to accumulate our result
|
reg [2*N-2:0] reg_working_result; // a place to accumulate our result
|
reg [2*N-2:0] reg_multiplier_temp; // a working copy of the multiplier
|
reg [2*N-2:0] reg_multiplier_temp; // a working copy of the multiplier
|
reg [N-1:0] reg_multiplicand_temp; // a working copy of the umultiplicand
|
reg [N-1:0] reg_multiplicand_temp; // a working copy of the umultiplicand
|
|
|
reg [N:0] reg_count; // This is obviously a lot bigger than it needs to be, as we only need
|
reg [N-1:0] reg_count; // This is obviously a lot bigger than it needs to be, as we only need
|
// count to N, but computing that number of bits requires a
|
// count to N, but computing that number of bits requires a
|
// logarithm (base 2), and I don't know how to do that in a
|
// logarithm (base 2), and I don't know how to do that in a
|
// way that will work for every possibility
|
// way that will work for every possibility
|
|
|
reg reg_done; // Computation completed flag
|
reg reg_done; // Computation completed flag
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.