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## Block Diagram
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# Wupper: A PCIe Gen3/Gen4 DMA controller for Xilinx FPGAs.
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The repository was moved to Nikhef Gitlab. Gitlab is expected to land on Opencores as well, until then Nikhef will be used.
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Please visit:
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https://gitlab.nikhef.nl/franss/wupper/
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## Description
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The Opencores page will be maintained to keep the project together
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Wupper is designed by [Nikhef](http://www.nikhef.nl) (Amsterdam, The Netherlands) for the CERN [ATLAS](http://atlas.cern) / [FELIX](https://atlas-project-felix.web.cern.ch/atlas-project-felix) project.
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Its main purpose is to provide a simple Direct Memory Access (DMA) interface to the Xilinx Virtex-7 PCIe Gen3 hard block.
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Wupper is specifically designed for the 256 bit wide AXI4-Stream interface of the [Xilinx Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)](https://www.xilinx.com/products/intellectual-property/7_series_gen_3_pci_express.html).
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Wupper has been also successfully ported to Xilinx Kintex UltraScale FPGAs.
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#### DMA read and write
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The main purpose of Wupper is therefore to provide an interface to standard FIFOs.
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This is the done by the _DMA\_read\_write_ block in the diagram above.
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The read/write FIFOs have the same width as the Xilinx AXI4-Stream interface (256 bits) and run at 250 MHz.
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The application side of the FPGA design can simply read or write the FIFOs.
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Wupper will handle the transfer to Host PC memory, according to the addresses specified in the _DMA descriptors_.
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#### DMA control
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Another functionality of Wupper is thus to manage a set of DMA descriptors.
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Descriptors consist of an address, a read/write flag, the transfer size (number of 32 bit words) and an enable line.
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Descriptors are handled by the _DMA\_control_ block.
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These descriptors are mapped as normal PCIe memory or IO registers.
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Besides the descriptors and the enable line (one per descriptor), a status register for every descriptor is provided in the register map.
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#### Generic register map
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Besides DMA specific functions, the DMA control block can also handle generic _control_ and _monitor_ registers for user application.
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#### Interrupt handler
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Wupper is provided with a generic MSI-X compatible interrupt controller.
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#### Implementation info
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For synthesis and implementation of the cores, it is recommend to use Xilinx Vivado 2014.2.
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Other IP cores (FIFO, clock wizard and PCIe) are provided in the Xilinx .xci format, as well as the constraints file (.xdc) is in the Vivado 2014.2 Format.
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Wupper is also known to work well with Vivado 2014.4, constraints will be updated.
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For portability reasons, no Xilinx project files will be supplied with Wupper.
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Instead, a bundle of _TCL scripts_ has been supplied to create a project and import all necessary files, as well as to do the synthesis and implementation.
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These scripts are be described in details in the [/documentation/wupper.pdf](http://opencores.org/websvn,filedetails?repname=virtex7_pcie_dma&path=%2Fvirtex7_pcie_dma%2Ftrunk%2Fdocumentation%2Fwupper.pdf) distributed with Wupper.
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## Feedback
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\>> Give comments and feedback using the official core thread on the OpenCores forum:
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[forum\_thread](http://opencores.org/forum,Cores,0,5580)
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The Opencores page will be maintained to keep the project together
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