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--!
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--!
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--! Copyright (C) 2011 - 2012 Creonic GmbH
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--! Copyright (C) 2011 - 2014 Creonic GmbH
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--!
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--!
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! under the terms of the GNU General Public License version 2.
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--! under the terms of the GNU General Public License version 2.
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--!
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--!
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--! @file
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--! @file
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signal rst : std_logic;
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signal rst : std_logic;
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-- split tdata into input array
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-- split tdata into input array
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signal input : t_input_block;
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signal input : t_input_block;
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-- buffer signals
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signal buffer_tdata : std_logic_vector(31 downto 0);
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signal buffer_tvalid : std_logic;
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signal buffer_tlast : std_logic;
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-- branch signals
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-- branch signals
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signal branch_tvalid : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
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signal branch_tvalid : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
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signal branch_tdata : t_branch;
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signal branch_tdata : t_branch;
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signal branch_tlast : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
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signal branch_tlast : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
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signal branch_tready : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
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signal branch_tready : std_logic_vector(NUMBER_BRANCH_UNITS - 1 downto 0);
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-- reorder signals
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-- reorder signals
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signal reorder_tready, reorder_tvalid : std_logic_vector(1 downto 0);
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signal reorder_tready, reorder_tvalid : std_logic_vector(1 downto 0);
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signal reorder_tdata, reorder_tlast : std_logic_vector(1 downto 0);
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signal reorder_tdata, reorder_tlast : std_logic_vector(1 downto 0);
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signal reorder_last_tuser : std_logic_vector(1 downto 0);
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signal reorder_last_tuser : std_logic_vector(1 downto 0);
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signal reorder_recursion_tvalid : std_logic;
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signal reorder_recursion_tdata : std_logic;
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signal reorder_recursion_tlast : std_logic;
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-- recursion signals
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signal recursion_tready : std_logic;
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-- output signals
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-- output signals
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signal output_tready : std_logic_vector(1 downto 0);
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signal output_tready : std_logic_vector(1 downto 0);
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signal current_active, semaphore_output : integer range 1 downto 0;
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signal current_active : integer range 1 downto 0;
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begin
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begin
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--
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--
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-- There is always one byte of data for each LLR value, even though each
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-- There is always one byte of data for each LLR value, even though each
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-- LLR value is represented with BW_LLR_INPUT bits. Hence, only
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-- LLR value is represented with BW_LLR_INPUT bits. Hence, only
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-- BW_LLR_INPUT bits are extracted from the byte.
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-- BW_LLR_INPUT bits are extracted from the byte.
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--
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--
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gen_input_assignment: for i in NUMBER_PARITY_BITS - 1 downto 0 generate
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gen_input_assignment: for i in NUMBER_PARITY_BITS - 1 downto 0 generate
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begin
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begin
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input(i) <= signed(s_axis_input_tdata(8 * i + BW_LLR_INPUT - 1 downto 8 * i));
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input(i) <= signed(buffer_tdata(8 * i + BW_LLR_INPUT - 1 downto 8 * i));
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end generate gen_input_assignment;
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end generate gen_input_assignment;
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rst <= not aresetn;
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rst <= not aresetn;
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------------------------------
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------------------------------
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--- Portmapping components ---
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--- Portmapping components ---
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------------------------------
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------------------------------
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-------------------------------------
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-------------------------------------
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-- AXI4S input buffer
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--------------------------------------
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inst_axi4s_buffer: axi4s_buffer
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generic map(
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DATA_WIDTH => 32
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)
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port map(
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clk => clk,
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rst => rst,
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input => s_axis_input_tdata,
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input_valid => s_axis_input_tvalid,
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input_last => s_axis_input_tlast,
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input_accept => s_axis_input_tready,
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output => buffer_tdata,
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output_valid => buffer_tvalid,
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output_last => buffer_tlast,
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output_accept => branch_tready(0)
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);
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-------------------------------------
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-- Branch metric unit
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-- Branch metric unit
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--------------------------------------
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--------------------------------------
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gen_branch_distance : for i in NUMBER_BRANCH_UNITS - 1 downto 0 generate
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gen_branch_distance : for i in NUMBER_BRANCH_UNITS - 1 downto 0 generate
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begin
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begin
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Line 171... |
)
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)
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port map(
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port map(
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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s_axis_input_tvalid => s_axis_input_tvalid,
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s_axis_input_tvalid => buffer_tvalid,
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s_axis_input_tdata => input,
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s_axis_input_tdata => input,
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s_axis_input_tlast => s_axis_input_tlast,
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s_axis_input_tlast => buffer_tlast,
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s_axis_input_tready => branch_tready(i),
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s_axis_input_tready => branch_tready(i),
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m_axis_output_tvalid => branch_tvalid(i),
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m_axis_output_tvalid => branch_tvalid(i),
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m_axis_output_tdata => branch_tdata(i),
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m_axis_output_tdata => branch_tdata(i),
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m_axis_output_tlast => branch_tlast(i),
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m_axis_output_tlast => branch_tlast(i),
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------------------------------
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------------------------------
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-- Recursive codes handling --
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-- Recursive codes handling --
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------------------------------
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------------------------------
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gen_inst_recursion : if FEEDBACK_POLYNOMIAL /= 0 generate
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gen_inst_recursion : if FEEDBACK_POLYNOMIAL /= 0 generate
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signal reorder_recursion_tvalid : std_logic;
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signal reorder_recursion_tdata : std_logic;
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signal reorder_recursion_tlast : std_logic;
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signal recursion_tready : std_logic;
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begin
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begin
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inst_recursion : recursion
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inst_recursion : recursion
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port map(
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port map(
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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m_axis_output_tvalid => m_axis_output_tvalid,
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m_axis_output_tvalid => m_axis_output_tvalid,
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m_axis_output_tdata => m_axis_output_tdata,
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m_axis_output_tdata => m_axis_output_tdata,
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m_axis_output_tlast => m_axis_output_tlast,
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m_axis_output_tlast => m_axis_output_tlast,
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m_axis_output_tready => m_axis_output_tready
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m_axis_output_tready => m_axis_output_tready
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);
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);
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end generate gen_inst_recursion;
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-------------------------------
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-------------------------------
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-- Input interface handling
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-- Output interface handling
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-------------------------------
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-------------------------------
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s_axis_input_tready <= branch_tready(0);
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reorder_recursion_tvalid <= '1' when reorder_tvalid(0) = '1' or reorder_tvalid(1) = '1' else
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'0';
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reorder_recursion_tdata <= reorder_tdata(0) when current_active = 0 else
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reorder_tdata(1);
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reorder_recursion_tlast <= '1' when reorder_tlast(0) = '1' or reorder_tlast(1) = '1' else
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'0';
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output_tready(0) <= '1' when (current_active = 0) and m_axis_output_tready = '1' else
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'0';
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output_tready(1) <= '1' when (current_active = 1) and m_axis_output_tready = '1' else
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'0';
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end generate gen_inst_recursion;
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no_recursion: if FEEDBACK_POLYNOMIAL = 0 generate
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-------------------------------
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-------------------------------
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-- Output interface handling
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-- Output interface handling
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-------------------------------
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-------------------------------
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no_recursion: if FEEDBACK_POLYNOMIAL = 0 generate
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m_axis_output_tdata <= reorder_tdata(0) when current_active = 0 else
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m_axis_output_tdata <= reorder_tdata(0) when reorder_tvalid(0) = '1' else
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reorder_tdata(1);
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reorder_tdata(1);
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m_axis_output_tvalid <= '1' when reorder_tvalid(0) = '1' or reorder_tvalid(1) = '1' else
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m_axis_output_tvalid <= '1' when reorder_tvalid(0) = '1' or reorder_tvalid(1) = '1' else
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'0';
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'0';
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m_axis_output_tlast <= '1' when reorder_tlast(0) = '1' or reorder_tlast(1) = '1' else
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m_axis_output_tlast <= '1' when reorder_tlast(0) = '1' or reorder_tlast(1) = '1' else
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'0';
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'0';
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output_tready(0) <= '1' when (semaphore_output = 1 or current_active = 0) and m_axis_output_tready = '1' else
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output_tready(0) <= '1' when (current_active = 0) and m_axis_output_tready = '1' else
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'0';
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'0';
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output_tready(1) <= '1' when (semaphore_output = 1 or current_active = 1) and m_axis_output_tready = '1' else
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output_tready(1) <= '1' when (current_active = 1) and m_axis_output_tready = '1' else
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'0';
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'0';
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end generate no_recursion;
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end generate no_recursion;
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recursion : if FEEDBACK_POLYNOMIAL /= 0 generate
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recursion : if FEEDBACK_POLYNOMIAL /= 0 generate
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begin
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begin
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reorder_recursion_tvalid <= '1' when reorder_tvalid(0) = '1' or reorder_tvalid(1) = '1' else
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'0';
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reorder_recursion_tdata <= reorder_tdata(0) when reorder_tvalid(0) = '1' else
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reorder_tdata(1);
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reorder_recursion_tlast <= '1' when reorder_tlast(0) = '1' or reorder_tlast(1) = '1' else
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'0';
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output_tready(0) <= '1' when (semaphore_output = 1 or current_active = 0) and recursion_tready = '1' else
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'0';
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output_tready(1) <= '1' when (semaphore_output = 1 or current_active = 1) and recursion_tready = '1' else
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'0';
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end generate recursion;
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end generate recursion;
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-- Check and merge reordering outputs and block if necessary.
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-- Check and merge reordering outputs and block if necessary.
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pr_reorder_tready : process(clk) is
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pr_reorder_tready : process(clk) is
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rst = '1' then
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if rst = '1' then
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current_active <= 0;
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current_active <= 0;
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semaphore_output <= 1;
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else
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else
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if reorder_last_tuser(current_active) = '1' then
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if reorder_tvalid(current_active) = '1' and m_axis_output_tready = '1' and reorder_last_tuser(current_active) = '1' then
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semaphore_output <= 1;
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current_active <= 1 - current_active;
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end if;
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if semaphore_output = 1 then
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if reorder_tvalid(0) = '1' then
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current_active <= 0;
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semaphore_output <= 0;
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end if;
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if reorder_tvalid(1) = '1' then
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current_active <= 1;
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semaphore_output <= 0;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process pr_reorder_tready;
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end process pr_reorder_tready;
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