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--!
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--!
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--! Copyright (C) 2011 - 2012 Creonic GmbH
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--! Copyright (C) 2011 - 2014 Creonic GmbH
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--!
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--!
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! under the terms of the GNU General Public License version 2.
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--! under the terms of the GNU General Public License version 2.
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--!
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--!
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--! @file
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--! @file
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end entity reorder;
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end entity reorder;
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architecture rtl of reorder is
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architecture rtl of reorder is
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-- used to store one reversed output of an traceback unit
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-- used to store one reversed output of a traceback unit
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signal buffer_sreg : unsigned(MAX_WINDOW_LENGTH - 1 downto 0);
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signal buffer_sreg : unsigned(MAX_WINDOW_LENGTH - 1 downto 0);
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signal buffer_cnt : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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signal buffer_cnt : unsigned(BW_MAX_WINDOW_LENGTH - 1 downto 0);
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signal buffer_end : integer range ENCODER_MEMORY_DEPTH downto 0;
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signal buffer_end : integer range ENCODER_MEMORY_DEPTH downto 0;
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signal send_output, last_window : boolean;
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signal send_output, last_window : boolean;
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s_axis_input_tready <= s_axis_input_tready_int;
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s_axis_input_tready <= s_axis_input_tready_int;
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s_axis_input_tready_int <= '1' when not(send_output) else
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s_axis_input_tready_int <= '1' when not(send_output) else
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'0';
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'0';
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m_axis_output_tvalid <= '1' when send_output and m_axis_output_tready= '1' else
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-- m_axis_output_tvalid <= '1' when send_output and m_axis_output_tready= '1' else
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m_axis_output_tvalid <= '1' when send_output else
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'0';
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'0';
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m_axis_output_tdata <= buffer_sreg(0);
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m_axis_output_tdata <= buffer_sreg(0);
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m_axis_output_tlast <= '1' when buffer_cnt = ENCODER_MEMORY_DEPTH and last_window else
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m_axis_output_tlast <= '1' when buffer_cnt = ENCODER_MEMORY_DEPTH and last_window else
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'0';
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'0';
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-- Reorder the global path given from an tracebackunit with the help of an shift register.
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-- Reorder the global path given from an traceback unit with the help of a shift register.
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pr_reorder : process(clk) is
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pr_reorder : process(clk) is
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rst = '1' then
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if rst = '1' then
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buffer_sreg <= (others => '0');
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buffer_sreg <= (others => '0');
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