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--!
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--!
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--! Copyright (C) 2011 - 2012 Creonic GmbH
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--! Copyright (C) 2011 - 2014 Creonic GmbH
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--!
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--!
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! under the terms of the GNU General Public License version 2.
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--! under the terms of the GNU General Public License version 2.
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--!
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--!
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--! @file
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--! @file
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entity tb_dec_viterbi is
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entity tb_dec_viterbi is
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generic(
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generic(
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CLK_PERIOD : time := 10 ns; -- Clock period within simulation.
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CLK_PERIOD : time := 10 ns; -- Clock period within simulation.
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BLOCK_LENGTH_START : natural := 200; -- First block length to simulate.
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BLOCK_LENGTH_START : natural := 200; -- First block length to simulate.
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BLOCK_LENGTH_END : natural := 300; -- Last block length to simulate.
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BLOCK_LENGTH_END : natural := 500; -- Last block length to simulate.
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BLOCK_LENGTH_INCR : integer := 100; -- Increment from one block length to another.
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BLOCK_LENGTH_INCR : integer := 20; -- Increment from one block length to another.
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SIM_ALL_BLOCKS : boolean := true; -- Set to true in order to simulate all blocks within a data file.
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SIM_ALL_BLOCKS : boolean := true; -- Set to true in order to simulate all blocks within a data file.
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SIM_BLOCK_START : natural := 396; -- If SIM_ALL_BLOCKS = false, gives block to start simulation with.
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SIM_BLOCK_START : natural := 0; -- If SIM_ALL_BLOCKS = false, gives block to start simulation with.
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SIM_BLOCK_END : natural := 398; -- If SIM_ALL_BLOCKS = false, gives last block of simulation.
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SIM_BLOCK_END : natural := 10; -- If SIM_ALL_BLOCKS = false, gives last block of simulation.
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WINDOW_LENGTH : natural := 55; -- Window length to use for simulation.
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WINDOW_LENGTH : natural := 55; -- Window length to use for simulation.
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ACQUISITION_LENGTH : natural := 50; -- Acquisition length to use for simulation.
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ACQUISITION_LENGTH : natural := 50; -- Acquisition length to use for simulation.
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DATA_DIRECTORY : string := "../testbench/WiFi_121_91/" -- Path to testbench data, relative to simulation directory.
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DATA_DIRECTORY : string := "../testbench/WiFi_121_91/" -- Path to testbench data, relative to simulation directory.
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Line 89... |
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--
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--
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-- Input data send signals.
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-- Input data send signals.
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--
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--
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type t_send_data_fsm is (READ_FILE, CONFIGURE, SEND_DATA, SEND_DATA_FINISHED);
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type t_send_data_fsm is (READ_FILE, CONFIGURE, SEND_DATA, DEASSERT_VALID, SEND_DATA_FINISHED, SEND_FIRST_DATA);
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signal send_data_fsm : t_send_data_fsm;
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signal send_data_fsm : t_send_data_fsm;
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signal block_send_end : natural;
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signal block_send_end : natural;
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signal current_block : natural;
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signal current_block : natural;
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| Line 113... |
Line 113... |
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signal first_block_out : natural;
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signal first_block_out : natural;
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signal last_block_out : natural;
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signal last_block_out : natural;
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signal current_block_out : natural;
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signal current_block_out : natural;
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signal current_block_length_out : natural;
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signal current_block_length_out : natural;
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signal current_block_length_out_d : natural;
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signal sys_bit_counter_out : natural;
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signal sys_bit_counter_out : natural;
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-- Get filename that matches to our current configuration.
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-- Get filename that matches to our current configuration.
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function get_filename_part(v_block_length : natural;
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function get_filename_part(v_block_length : natural;
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Line 127... |
return "BL_" & str(v_block_length) & "_WL_" & str(v_window_length) & "_AL_" & str(v_acquisition_length);
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return "BL_" & str(v_block_length) & "_WL_" & str(v_window_length) & "_AL_" & str(v_acquisition_length);
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end function get_filename_part;
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end function get_filename_part;
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shared variable v_decoded_software : t_nat_array_ptr;
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shared variable v_decoded_software : t_nat_array_ptr;
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signal valid_cnt : natural :=0;
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signal ready_cnt : natural :=0;
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begin
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begin
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clk <= not clk after CLK_PERIOD / 2;
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clk <= not clk after CLK_PERIOD / 2;
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Line 151... |
variable v_llr : t_int_array_ptr;
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variable v_llr : t_int_array_ptr;
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variable v_filepart_ptr : t_string_ptr;
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variable v_filepart_ptr : t_string_ptr;
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variable v_filename_ptr : t_string_ptr;
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variable v_filename_ptr : t_string_ptr;
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variable v_num_lines : natural := 0;
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variable v_num_lines : natural := 0;
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variable v_num_blocks : natural := 0;
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variable v_num_blocks : natural := 0;
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variable v_current_block_length : natural := 0;
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variable v_sys_bit_counter : integer := 0;
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if aresetn = '0' then
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if aresetn = '0' then
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-- ctrl_tlast is present but unused in the decoder
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-- ctrl_tlast is present but unused in the decoder
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Line 171... |
current_block <= 0;
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current_block <= 0;
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block_send_end <= 0;
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block_send_end <= 0;
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sys_bit_counter <= 0;
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sys_bit_counter <= 0;
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send_data_fsm <= READ_FILE;
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send_data_fsm <= READ_FILE;
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valid_cnt <= 0;
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else
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else
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case send_data_fsm is
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case send_data_fsm is
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Line 219... |
std_logic_vector(to_unsigned(ACQUISITION_LENGTH, BW_MAX_WINDOW_LENGTH));
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std_logic_vector(to_unsigned(ACQUISITION_LENGTH, BW_MAX_WINDOW_LENGTH));
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-- Check whether configuration succeeded
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-- Check whether configuration succeeded
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if m_axis_ctrl_tvalid = '1' and m_axis_ctrl_tready = '1' then
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if m_axis_ctrl_tvalid = '1' and m_axis_ctrl_tready = '1' then
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m_axis_ctrl_tvalid <= '0';
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m_axis_ctrl_tvalid <= '0';
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send_data_fsm <= SEND_DATA;
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send_data_fsm <= SEND_FIRST_DATA;
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else
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else
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m_axis_ctrl_tvalid <= '1';
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m_axis_ctrl_tvalid <= '1';
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end if;
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end if;
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when SEND_FIRST_DATA =>
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for j in 0 to NUMBER_PARITY_BITS - 1 loop
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m_axis_input_tdata(j * 8 + BW_LLR_INPUT - 1 downto j * 8) <=
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std_logic_vector(to_signed(v_llr(current_block * (current_block_length_tail * NUMBER_PARITY_BITS) + sys_bit_counter * NUMBER_PARITY_BITS + j), BW_LLR_INPUT));
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end loop;
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sys_bit_counter <= sys_bit_counter + 1;
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send_data_fsm <= SEND_DATA;
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m_axis_input_tvalid <= '1';
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--
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--
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-- Send all data of a block. If we are done with this, we check what to do next:
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-- Send all data of a block. If we are done with this, we check what to do next:
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-- 1) Configure the decoder to process the next block of the same length.
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-- 1) Configure the decoder to process the next block of the same length.
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-- 2) Read a new file if all blocks of this block length were simulated.
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-- 2) Read a new file if all blocks of this block length were simulated.
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Line 246... |
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m_axis_input_tvalid <= '1';
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m_axis_input_tvalid <= '1';
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-- Data transmission => increase bit counter and update data for next cycle.
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-- Data transmission => increase bit counter and update data for next cycle.
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if m_axis_input_tvalid = '1' and m_axis_input_tready = '1' then
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if m_axis_input_tvalid = '1' and m_axis_input_tready = '1' then
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v_sys_bit_counter := sys_bit_counter + 1;
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if valid_cnt = 5 then
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sys_bit_counter <= v_sys_bit_counter;
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valid_cnt <= 0;
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send_data_fsm <= DEASSERT_VALID;
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m_axis_input_tvalid <= '0';
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else
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else
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v_sys_bit_counter := sys_bit_counter;
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valid_cnt <= valid_cnt + 1;
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end if;
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sys_bit_counter <= sys_bit_counter + 1;
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end if;
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end if;
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if v_sys_bit_counter < current_block_length_tail then
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if m_axis_input_tvalid = '1' and m_axis_input_tready = '1' then
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if sys_bit_counter < current_block_length_tail then
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-- trim and move data to stream
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-- trim and move data to stream
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for j in 0 to NUMBER_PARITY_BITS - 1 loop
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for j in 0 to NUMBER_PARITY_BITS - 1 loop
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m_axis_input_tdata(j * 8 + BW_LLR_INPUT - 1 downto j * 8) <=
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m_axis_input_tdata(j * 8 + BW_LLR_INPUT - 1 downto j * 8) <=
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std_logic_vector(to_signed(v_llr(current_block * (current_block_length_tail * NUMBER_PARITY_BITS) + v_sys_bit_counter * NUMBER_PARITY_BITS + j), BW_LLR_INPUT));
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std_logic_vector(to_signed(v_llr(current_block * (current_block_length_tail * NUMBER_PARITY_BITS) + sys_bit_counter * NUMBER_PARITY_BITS + j), BW_LLR_INPUT));
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end loop;
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end loop;
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end if;
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end if;
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-- Next data will be last of block
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-- Next data will be last of block
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if v_sys_bit_counter = current_block_length_tail - 1 then
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if sys_bit_counter = current_block_length_tail - 1 then
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m_axis_input_tlast <= '1';
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m_axis_input_tlast <= '1';
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else
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else
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m_axis_input_tlast <= '0';
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m_axis_input_tlast <= '0';
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end if;
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end if;
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end if;
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-- We have just sent the very last bit of this block.
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-- We have just sent the very last bit of this block.
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if m_axis_input_tvalid = '1' and
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if m_axis_input_tvalid = '1' and m_axis_input_tready = '1' and
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m_axis_input_tready = '1' and
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m_axis_input_tlast = '1' then
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m_axis_input_tlast = '1' then
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-- if v_sys_bit_counter = current_block_length then
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sys_bit_counter <= 0;
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sys_bit_counter <= 0;
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m_axis_input_tvalid <= '0';
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m_axis_input_tvalid <= '0';
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-- Did we process the last block of a block length?
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-- Did we process the last block of a block length?
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if current_block = block_send_end then
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if current_block = block_send_end then
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Line 298... |
send_data_fsm <= CONFIGURE;
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send_data_fsm <= CONFIGURE;
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current_block <= current_block + 1;
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current_block <= current_block + 1;
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end if;
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end if;
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end if;
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end if;
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when DEASSERT_VALID =>
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send_data_fsm <= SEND_DATA;
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--
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--
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-- We are done with all blocks, do nothing anynmore.
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-- We are done with all blocks, do nothing anynmore.
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--
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--
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when SEND_DATA_FINISHED =>
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when SEND_DATA_FINISHED =>
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Line 325... |
begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if aresetn = '0' then
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if aresetn = '0' then
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current_block_length_out <= 0;
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current_block_length_out <= 0;
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current_block_length_out_d <= 0;
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sys_bit_counter_out <= 0;
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sys_bit_counter_out <= 0;
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s_axis_output_tready <= '1';
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s_axis_output_tready <= '1';
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block_receive_complete <= false;
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block_receive_complete <= false;
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new_block_length <= false;
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new_block_length <= false;
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ready_cnt <= 0;
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else
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else
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block_receive_complete <= false;
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block_receive_complete <= false;
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new_block_length <= false;
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new_block_length <= false;
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current_block_length_out_d <= current_block_length_out;
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s_axis_output_tready <= '1';
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-- Data passes the output interface.
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-- Data passes the output interface.
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if s_axis_output_tvalid = '1' and s_axis_output_tready = '1' then
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if s_axis_output_tvalid = '1' and s_axis_output_tready = '1' then
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if ready_cnt = 8 then
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ready_cnt <= 0;
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s_axis_output_tready <= '0';
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else
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ready_cnt <= ready_cnt + 1;
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end if;
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decoded_hardware(sys_bit_counter_out) <= s_axis_output_tdata;
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decoded_hardware(sys_bit_counter_out) <= s_axis_output_tdata;
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sys_bit_counter_out <= sys_bit_counter_out + 1;
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sys_bit_counter_out <= sys_bit_counter_out + 1;
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| Line 345... |
Line 366... |
v_num_lines := get_num_lines(v_filename_ptr.all);
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v_num_lines := get_num_lines(v_filename_ptr.all);
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read_file(v_decoded_software, v_num_lines, BW_LLR_INPUT, v_filename_ptr.all);
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read_file(v_decoded_software, v_num_lines, BW_LLR_INPUT, v_filename_ptr.all);
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if SIM_ALL_BLOCKS then
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if SIM_ALL_BLOCKS then
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first_block_out <= 0;
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first_block_out <= 0;
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last_block_out <= v_num_lines / (sys_bit_counter_out + 1);
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last_block_out <= v_num_lines / (sys_bit_counter_out + 1) - 1;
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else
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else
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first_block_out <= SIM_BLOCK_START;
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first_block_out <= SIM_BLOCK_START;
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last_block_out <= SIM_BLOCK_END;
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last_block_out <= SIM_BLOCK_END;
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end if;
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end if;
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| Line 394... |
Line 415... |
(v_decoded_software(v_current_block * current_block_length_out + i) = 1 and decoded_hardware(i) = '0') then
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(v_decoded_software(v_current_block * current_block_length_out + i) = 1 and decoded_hardware(i) = '0') then
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v_bit_error_count := v_bit_error_count + 1;
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v_bit_error_count := v_bit_error_count + 1;
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assert false report "Decoded bit " & str(i) & " in block " & str(v_current_block) & " does not match!"
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assert false report "Decoded bit " & str(i) & " in block " & str(v_current_block) & " does not match!"
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severity warning;
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severity failure;
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end if;
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end if;
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end loop;
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end loop;
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-- Dump message.
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-- Dump message.
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write(v_line_out, string'("Block length: ") & str(current_block_length_out));
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write(v_line_out, string'("Block length: ") & str(current_block_length_out));
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write(v_line_out, string'(", Block: ") & str(current_block_out));
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write(v_line_out, string'(", Block: ") & str(v_current_block));
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write(v_line_out, string'(", errors: ") & str(v_bit_error_count));
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write(v_line_out, string'(", errors: ") & str(v_bit_error_count));
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writeline(output, v_line_out);
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if current_block_out /= last_block_out - 1 then
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current_block_out <= current_block_out + 1;
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current_block_out <= current_block_out + 1;
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else
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if current_block_out = last_block_out then
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current_block_out <= 0;
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current_block_out <= 0;
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-- Stop simulation, if we are done with all blocks of all block lengths.
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-- Stop simulation, if we are done with all blocks of all block lengths.
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if current_block_length_out = BLOCK_LENGTH_END then
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if current_block_length_out = BLOCK_LENGTH_END then
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assert false report "End" severity failure;
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assert false report "Simulation finished with no errors." severity failure;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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