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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbpwmaudio.v
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// Filename: wbpwmaudio.v
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//
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//
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// Project: A Wishbone Controlled PWM (audio) controller
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// Project: A Wishbone Controlled PWM (audio) controller
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//
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//
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// controller, to keep that from bothering you as well.
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// controller, to keep that from bothering you as well.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module wbpwmaudio(i_clk,
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//
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//
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`default_nettype none
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//
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module wbpwmaudio(i_clk, i_reset,
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// Wishbone interface
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// Wishbone interface
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_pwm, o_aux, o_int);
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o_pwm, o_aux, o_int);
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parameter DEFAULT_RELOAD = 17'd1814, // about 44.1 kHz @ 80MHz
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parameter DEFAULT_RELOAD = 16'd1814, // about 44.1 kHz @ 80MHz
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//DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz
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//DEFAULT_RELOAD = 16'd2268,//about 44.1 kHz @ 100MHz
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NAUX=2, // Dev control values
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NAUX=2, // Dev control values
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VARIABLE_RATE=0,
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VARIABLE_RATE=0,
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TIMING_BITS=17;
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TIMING_BITS=16;
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input i_clk;
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input wire i_clk, i_reset;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input wire i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_addr;
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input wire i_wb_addr;
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input [31:0] i_wb_data;
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input wire [31:0] i_wb_data;
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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output reg o_pwm;
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output reg o_pwm;
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output reg [(NAUX-1):0] o_aux;
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output reg [(NAUX-1):0] o_aux;
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output reg o_int;
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output wire o_int;
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// How often shall we create an interrupt? Every reload_value clocks!
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// How often shall we create an interrupt? Every reload_value clocks!
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// If VARIABLE_RATE==0, this value will never change and will be kept
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// If VARIABLE_RATE==0, this value will never change and will be kept
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// at the default reload rate (defined up top)
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// at the default reload rate (defined up top)
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if (VARIABLE_RATE != 0)
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if (VARIABLE_RATE != 0)
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begin
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begin
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reg [(TIMING_BITS-1):0] r_reload_value;
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reg [(TIMING_BITS-1):0] r_reload_value;
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initial r_reload_value = DEFAULT_RELOAD;
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initial r_reload_value = DEFAULT_RELOAD;
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always @(posedge i_clk) // Data write
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always @(posedge i_clk) // Data write
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
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if ((i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
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r_reload_value <= i_wb_data[(TIMING_BITS-1):0];
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r_reload_value <= i_wb_data[(TIMING_BITS-1):0] - 1'b1;
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assign w_reload_value = r_reload_value;
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assign w_reload_value = r_reload_value;
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end else begin
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end else begin
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assign w_reload_value = DEFAULT_RELOAD;
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assign w_reload_value = DEFAULT_RELOAD;
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end endgenerate
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end endgenerate
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//
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// The next value timer
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//
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// We'll want a new sample every w_reload_value clocks. When the
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// timer hits zero, the signal ztimer (zero timer) will also be
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// set--allowing following logic to depend upon it.
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//
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reg ztimer;
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reg [(TIMING_BITS-1):0] timer;
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reg [(TIMING_BITS-1):0] timer;
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initial timer = DEFAULT_RELOAD;
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initial timer = DEFAULT_RELOAD;
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initial ztimer= 1'b0;
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always @(posedge i_clk)
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if (i_reset)
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ztimer <= 1'b0;
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else
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ztimer <= (timer == { {(TIMING_BITS-1){1'b0}}, 1'b1 });
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (timer == 0)
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if ((ztimer)||(i_reset))
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timer <= w_reload_value;
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timer <= w_reload_value;
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else
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else
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timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1};
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timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1};
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//
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// Whenever the timer runs out, accept the next value from the single
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// sample buffer.
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//
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reg [15:0] sample_out;
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reg [15:0] sample_out;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (timer == 0)
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if (ztimer)
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sample_out <= next_sample;
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sample_out <= next_sample;
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//
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// Control what's in the single sample buffer, next_sample, as well as
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// whether or not it's a valid sample. Specifically, if next_valid is
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// false, then the sample buffer needs a new value. Once the buffer
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// has a value within it, further writes will just quietly overwrite
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// this value.
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reg [15:0] next_sample;
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reg [15:0] next_sample;
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reg next_valid;
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reg next_valid;
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initial next_valid = 1'b1;
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initial next_valid = 1'b1;
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initial next_sample = 16'h8000;
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initial next_sample = 16'h8000;
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always @(posedge i_clk) // Data write
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always @(posedge i_clk) // Data write
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)
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if ((i_wb_stb)&&(i_wb_we)
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&&((~i_wb_addr)||(VARIABLE_RATE==0)))
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&&((!i_wb_addr)||(VARIABLE_RATE==0)))
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begin
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begin
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// Write with two's complement data, convert it
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// Write with two's complement data, convert it
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// internally to binary offset
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// internally to an unsigned binary offset
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next_sample <= { ~i_wb_data[15], i_wb_data[14:0] };
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// representation
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next_sample <= { !i_wb_data[15], i_wb_data[14:0] };
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next_valid <= 1'b1;
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next_valid <= 1'b1;
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if (i_wb_data[16])
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if (i_wb_data[16])
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o_aux <= i_wb_data[(NAUX+20-1):20];
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o_aux <= i_wb_data[(NAUX+20-1):20];
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end else if (timer == 0)
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end else if (ztimer)
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next_valid <= 1'b0;
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next_valid <= 1'b0;
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initial o_int = 1'b0;
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// If the value in our sample buffer isn't valid, create an interrupt
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always @(posedge i_clk)
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// that can be sent to a processor to know when to send a new sample.
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o_int <= (~next_valid);
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// This output can also be used to control a read from a FIFO as well,
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// depending on how you wish to use the core.
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assign o_int = (!next_valid);
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//
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// To generate our waveform, we'll compare our sample value against
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// a bit reversed counter. This counter is kept in pwm_counter.
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// The choice of a 16-bit counter is arbitrary, but it was made to
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// match the sixteen bits of the input
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reg [15:0] pwm_counter;
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reg [15:0] pwm_counter;
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initial pwm_counter = 16'h00;
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initial pwm_counter = 16'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_reset)
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pwm_counter <= 16'h0;
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else
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pwm_counter <= pwm_counter + 16'h01;
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pwm_counter <= pwm_counter + 16'h01;
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// Bit-reverse the counter
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wire [15:0] br_counter;
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wire [15:0] br_counter;
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genvar k;
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genvar k;
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generate for(k=0; k<16; k=k+1)
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generate for(k=0; k<16; k=k+1)
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begin : bit_reversal_loop
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begin : bit_reversal_loop
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assign br_counter[k] = pwm_counter[15-k];
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assign br_counter[k] = pwm_counter[15-k];
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end endgenerate
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end endgenerate
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// Apply our comparison to determine the next output bit
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_pwm <= (sample_out >= br_counter);
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o_pwm <= (sample_out >= br_counter);
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//
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// Handle the bus return traffic.
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generate
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generate
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if (VARIABLE_RATE == 0)
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if (VARIABLE_RATE == 0)
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begin
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begin
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// If we are running off of a fixed rate, then just return
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// the current setting of the aux registers, the current
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// interrupt value, and the current sample we are outputting.
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assign o_wb_data = { {(12-NAUX){1'b0}}, o_aux,
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assign o_wb_data = { {(12-NAUX){1'b0}}, o_aux,
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3'h0, o_int, sample_out };
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3'h0, o_int, sample_out };
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end else begin
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end else begin
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// On the other hand, if we have been built to support a
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// variable sample rate, then return the reload value for
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// address one but otherwise the data value (above) for address
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// zero.
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reg [31:0] r_wb_data;
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reg [31:0] r_wb_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_wb_addr)
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if (i_wb_addr)
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r_wb_data <= w_reload_value;
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r_wb_data <= { (32-TIMING_BITS),w_reload_value};
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else
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else
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r_wb_data <= { {(12-NAUX){1'b0}}, o_aux,
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r_wb_data <= { {(12-NAUX){1'b0}}, o_aux,
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3'h0, o_int, sample_out };
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3'h0, o_int, sample_out };
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assign o_wb_data = r_wb_data;
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assign o_wb_data = r_wb_data;
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end endgenerate
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end endgenerate
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// Always ack on the clock following any request
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initial o_wb_ack = 1'b0;
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initial o_wb_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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o_wb_ack <= (i_wb_stb);
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// Never stall
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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// Make Verilator happy. Since we aren't using all of the bits from
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// the bus, Verilator -Wall will complain. This just informs
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// V*rilator that we already know these bits aren't being used.
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//
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// verilator lint_off UNUSED
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wire [14:0] unused;
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assign unused = { i_wb_cyc, i_wb_data[31:21], i_wb_data[19:17] };
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// verilator lint_on UNUSED
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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