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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\documentclass{gqtekspec}
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\documentclass{gqtekspec}
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\project{Wishbone Scope}
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\project{Wishbone Scope}
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\title{Specification}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq (at) opencores.org}
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\email{dgisselq (at) ieee.org}
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\revision{Rev.~0.1}
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\revision{Rev.~0.1}
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\begin{document}
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\begin{document}
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\pagestyle{gqtekspecplain}
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\pagestyle{gqtekspecplain}
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\titlepage
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\titlepage
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\begin{license}
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\begin{license}
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ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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for more details.
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|
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see \hbox{<http://www.gnu.org/licenses/>} for a
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with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a
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copy.
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copy.
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\end{license}
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\end{license}
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\begin{revisionhistory}
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\begin{revisionhistory}
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0.3 & 6/22/2015 & Gisselquist & Minor updates to enhance readability \\\hline
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0.3 & 6/22/2015 & Gisselquist & Minor updates to enhance readability \\\hline
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0.2 & 6/22/2015 & Gisselquist & Finished Draft \\\hline
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0.2 & 6/22/2015 & Gisselquist & Finished Draft \\\hline
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What this table doesn't show is that all accesses to the port take a single
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What this table doesn't show is that all accesses to the port take a single
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clock. That is, if the {\tt i\_wb\_stb} line is high on one clock, the
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clock. That is, if the {\tt i\_wb\_stb} line is high on one clock, the
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{\tt i\_wb\_ack} line will be high the next. Further, the {\tt o\_wb\_stall}
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{\tt i\_wb\_ack} line will be high the next. Further, the {\tt o\_wb\_stall}
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line is tied to zero.
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line is tied to zero.
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\chapter{IO Ports}
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\chapter{I/O Ports}\label{ch:ioports}
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The ports are listed in Table.~\ref{tbl:ioports}.
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The ports are listed in Table.~\ref{tbl:ioports}.
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\begin{table}[htbp]
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\begin{table}[htbp]
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\begin{center}
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\begin{center}
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\begin{portlist}
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\begin{portlist}
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