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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [fault_sm.v] - Diff between revs 7 and 12

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Rev 7 Rev 12
Line 71... Line 71...
reg    [1:0]  seq_type;
reg    [1:0]  seq_type;
 
 
reg    [1:0]  seq_add;
reg    [1:0]  seq_add;
 
 
/*AUTOWIRE*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
 
// End of automatics
 
 
 
 
 
parameter [1:0]
parameter [1:0]
             SM_INIT       = 2'd0,
             SM_INIT       = 2'd0,
             SM_COUNT      = 2'd1,
             SM_COUNT      = 2'd1,

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