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https://opencores.org/ocsvn/xge_mac/xge_mac/trunk
[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [generic_mem_small.v] - Diff between revs 22 and 25
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| Rev 22 |
Rev 25 |
| Line 139... |
Line 139... |
end
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end
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end
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end
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`else
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`else
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always @(posedge rclk or negedge rrst_n)
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//always @(posedge rclk or negedge rrst_n)
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//begin
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// if (!rrst_n) begin
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// mem_rdata <= {(DWIDTH){1'b0}};
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// end else if (ren) begin
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// mem_rdata <= mem[raddr[AWIDTH-1:0]];
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// end
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//end
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always @(posedge rclk)
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begin
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begin
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if (!rrst_n) begin
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if (ren) begin
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mem_rdata <= {(DWIDTH){1'b0}};
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raddr_d1 <= raddr;
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end else if (ren) begin
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end
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mem_rdata <= mem[raddr[AWIDTH-1:0]];
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end
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end
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always @(raddr_d1, rclk)
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begin
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mem_rdata = mem[raddr_d1[AWIDTH-1:0]];
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end
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end
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`endif
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`endif
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