URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [rx_dequeue.v] - Diff between revs 7 and 12

Rev 7	Rev 12
Line 82...	Line 82...
`// End of automatics`	`// End of automatics`

`reg end_eop;`	`reg end_eop;`

`/AUTOWIRE/`	`/AUTOWIRE/`
`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
`// End of automatics`


`// End eop to force one cycle between packets`	`// End eop to force one cycle between packets`

`assign rxdfifo_ren = !rxdfifo_rempty && pkt_rx_ren && !end_eop;`	`assign rxdfifo_ren = !rxdfifo_rempty && pkt_rx_ren && !end_eop;`
Line 131...	Line 129...

`pkt_rx_val <= rxdfifo_ren;`	`pkt_rx_val <= rxdfifo_ren;`

`if (rxdfifo_ren) begin`	`if (rxdfifo_ren) begin`

	`ifdef BIGENDIAN
	`pkt_rx_data <= {rxdfifo_rdata[7:0],`
	`rxdfifo_rdata[15:8],`
	`rxdfifo_rdata[23:16],`
	`rxdfifo_rdata[31:24],`
	`rxdfifo_rdata[39:32],`
	`rxdfifo_rdata[47:40],`
	`rxdfifo_rdata[55:48],`
	`rxdfifo_rdata[63:56]};`
	`else
`pkt_rx_data <= rxdfifo_rdata;`	`pkt_rx_data <= rxdfifo_rdata;`
	`endif

`end`	`end`


if (rxdfifo_ren && rxdfifo_rstatus[`RXSTATUS_SOP]) begin	if (rxdfifo_ren && rxdfifo_rstatus[`RXSTATUS_SOP]) begin
Line 193...	Line 202...
`end`	`end`
`end`	`end`

`endmodule`	`endmodule`


`No newline at end of file`	`No newline at end of file`