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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [rx_enqueue.v] - Diff between revs 7 and 12

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Rev 7 Rev 12
Line 44... Line 44...
  rxhfifo_wdata, rxhfifo_wstatus, rxhfifo_wen, local_fault_msg_det,
  rxhfifo_wdata, rxhfifo_wstatus, rxhfifo_wen, local_fault_msg_det,
  remote_fault_msg_det, status_crc_error_tog,
  remote_fault_msg_det, status_crc_error_tog,
  status_fragment_error_tog, status_rxdfifo_ovflow_tog,
  status_fragment_error_tog, status_rxdfifo_ovflow_tog,
  status_pause_frame_rx_tog,
  status_pause_frame_rx_tog,
  // Inputs
  // Inputs
  clk_xgmii_rx, reset_xgmii_rx_n, xgmii_rxd, xgmii_rxc,
  clk_xgmii_rx, reset_xgmii_rx_n, xgmii_rxd, xgmii_rxc, rxdfifo_wfull,
  rxdfifo_wfull, rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty,
  rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty,
  rxhfifo_ralmost_empty
  rxhfifo_ralmost_empty
  );
  );
 
 
`include "CRC32_D64.v"
`include "CRC32_D64.v"
`include "CRC32_D8.v"
`include "CRC32_D8.v"
Line 106... Line 106...
reg                     status_pause_frame_rx_tog;
reg                     status_pause_frame_rx_tog;
reg                     status_rxdfifo_ovflow_tog;
reg                     status_rxdfifo_ovflow_tog;
// End of automatics
// End of automatics
 
 
/*AUTOWIRE*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
 
// End of automatics
 
 
 
 
 
reg [63:32]   xgmii_rxd_d1;
reg [63:32]   xgmii_rxd_d1;
reg [7:4]     xgmii_rxc_d1;
reg [7:4]     xgmii_rxc_d1;
 
 

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